Datasheet ADA4320-1 (Analog Devices)

ПроизводительAnalog Devices
Описание5 V DOCSIS 3.0 Low-distortion Upstream CATV Line Driver
Страниц / Страница16 / 1 — FEATURES. FUNCTIONAL BLOCK DIAGRAM. Supports CableLabs® DOCSIS 3.0/2.0 …
ВерсияA
Формат / Размер файлаPDF / 365 Кб
Язык документаанглийский

FEATURES. FUNCTIONAL BLOCK DIAGRAM. Supports CableLabs® DOCSIS 3.0/2.0 and EuroDOCSIS

Datasheet ADA4320-1 Analog Devices, Версия: A

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Low Distortion, DOCSIS 3.0, Upstream CATV Line Driver ADA4320-1
FEATURES FUNCTIONAL BLOCK DIAGRAM Supports CableLabs® DOCSIS 3.0/2.0 and EuroDOCSIS 3.0/2.0 specifications for customer premises equipment VIN– VOUT+ DIFF OR (CPE) upstream transmission ATTENUATION POWER SINGLE VERNIER CORE AMP INPUT 5 V single-supply operation AMP VIN+ VOUT– Z Excellent adjacent channel rejection performance 8 OUT DIFF = 300Ω ZIN (SINGLE) = 320Ω DECODE −66 dBc ACPR for a single QPSK channel ZIN (DIFF) = 640Ω 8 −63 dBc ACPR for 4× QAM64 channels POWER-DOWN RAMP DATA LATCH LOGIC Gain programmable in 1 dB steps over a 59 dB range 8 ADA4320-1 Gain range: −27 dB to +32 dB SHIFT REGISTER Current-scaled output stage
001
Low between-burst output noise level GND DATEN SDATA CLK TXEN SLEEP
08707-
−70 dB mV in 160 kHz bandwidth
Figure 1.
Maintains constant output impedance in enable, disable, and sleep conditions Selectable low power modes 12 mA in Tx disable 12 μA in sleep mode (full power-down) 3-wire, SPI-compatible interface 4 mm × 5 mm 24-lead LFCSP, RoHS compliant APPLICATIONS DOCSIS 3.0 and EuroDOCSIS cable modems/E-MTAs DOCSIS 3.0 set-top boxes CATV telephony modems Coaxial or twisted pair line drivers GENERAL DESCRIPTION
The ADA4320-1 is a high power, ultralow distortion amplifier The ADA4320-1 features an output driver stage that scales designed for CATV reverse channel line driving. Its features and quiescent current consumption according to gain setting. In specifications make the ADA4320-1 ideally suited for DOCSIS 3.0- multichannel mode at maximum gain (32 dB), the device draws and EuroDOCSIS 3.0-based applications. Both gain and output 260 mA from a single 5 V supply, enabling the high power, stage current are controlled via a 3-wire (SPI-compatible) interface. ultralow distortion performance required by multiple DOCSIS 3.0 A single 8-bit serial word selects one of four available supply upstream channels. For lifeline E-MTA applications, the ADA4320-1 current presets and one of sixty gain codes. output stage current can be throttled via SPI commands, reducing the power requirement for single-channel transmission by up to The ADA4320-1 has been tailored to address both the high output 30%. In transmit-disable mode, the ADA4320-1 draws only 12 mA. drive and stringent fidelity requirements of DOCSIS 3.0. The The device also features a full power-down sleep mode that part is able to maintain excellent adjacent channel rejection further reduces current draw to12 μA typical. performance over the full 5 MHz to 85 MHz range, even with multiple bonded channels at maximum specified output levels. The ADA4320-1 is packaged in a RoHS-compliant, 24-lead exposed pad LFCSP and is rated for operation over the −40°C The ADA4320-1 accepts a differential or single-ended input to +85°C temperature range. signal. The output is specified for driving a single-ended 75 Ω load through a 4:1 impedance transformer.
Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 www.analog.com Trademarks and registered trademarks are the property of their respective owners. Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE
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