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Datasheet ADA4320-1 (Analog Devices) - 2

ПроизводительAnalog Devices
ОписаниеLow Distortion, DOCSIS 3.0, Upstream CATV Line Driver
Страниц / Страница16 / 2 — REVISION HISTORY. 10/10—Rev. 0 to Rev. A. 4/10—Revision 0: Initial Version
ВерсияA
Формат / Размер файлаPDF / 365 Кб
Язык документаанглийский

REVISION HISTORY. 10/10—Rev. 0 to Rev. A. 4/10—Revision 0: Initial Version

REVISION HISTORY 10/10—Rev 0 to Rev A 4/10—Revision 0: Initial Version

Выбираем схему BMS для заряда литий-железофосфатных (LiFePO4) аккумуляторов

Модельный ряд для этого даташита

Текстовая версия документа

link to page 1 link to page 1 link to page 1 link to page 1 link to page 2 link to page 3 link to page 4 link to page 5 link to page 6 link to page 6 link to page 6 link to page 6 link to page 7 link to page 8 link to page 11 link to page 11 link to page 11 link to page 11 link to page 11 link to page 12 link to page 12 link to page 12 link to page 12 link to page 12 link to page 12 link to page 13 link to page 13 link to page 14 link to page 14 ADA4320-1 TABLE OF CONTENTS Features .. 1 General Applications ... 11 Applications ... 1 Circuit Description .. 11 Functional Block Diagram .. 1 Programming .. 11 General Description ... 1 Current Level and Gain Adjustment ... 11 Revision History ... 2 Power Saving Features ... 12 Specifications ... 3 Input Bias, Impedance, and Termination .. 12 Logic Inputs (TTL-/CMOS-Compatible Logic) ... 4 Output Bias, Impedance, and Termination .. 12 Timing Requirements .. 5 Power Supply ... 12 Absolute Maximum Ratings .. 6 Signal Integrity Layout Considerations ... 12 Thermal Resistance .. 6 Initial Power-Up ... 12 Maximum Power Dissipation ... 6 RAMP Pin Feature ... 13 ESD Caution .. 6 Output Transformer ... 13 Pin Configuration and Function Descriptions ... 7 Outline Dimensions ... 14 Typical Performance Characteristics ... 8 Ordering Guide .. 14 Applications Information .. 11
REVISION HISTORY 10/10—Rev. 0 to Rev. A
Changes to Product Title ... 1 Changes to Pin 14, Description, Table 6 .. 7 Changes to Current Level and Gain Adjustment Section ... 11 Changes to Output Bias, Impedance, and Termination Section ... 12 Changes to Figure 24 .. 13 Changes to Ordering Guide .. 14
4/10—Revision 0: Initial Version
Rev. A | Page 2 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE MAXIMUM POWER DISSIPATION ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION PROGRAMMING CURRENT LEVEL AND GAIN ADJUSTMENT POWER SAVING FEATURES INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN FEATURE OUTPUT TRANSFORMER OUTLINE DIMENSIONS ORDERING GUIDE
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