AD5522Data SheetGENERAL DESCRIPTION The AD5522 is a high performance, highly integrated parametric The PMU functions are control ed via a simple 3-wire serial measurement unit consisting of four independent channels. Each interface compatible with SPI, QSPI™, MICROWIRE™, and DSP per-pin parametric measurement unit (PPMU) channel includes interface standards. Interface clocks of 50 MHz allow fast updating five 16-bit, voltage output DACs that set the programmable input of modes. The low voltage differential signaling (LVDS) interface levels for the force voltage inputs, clamp inputs, and comparator protocol at 83 MHz is also supported. Comparator outputs are inputs (high and low). Five programmable force and measure provided per channel for device go-no-go testing and character- current ranges are available, ranging from ±5 µA to ±80 mA. ization. Control registers allow the user to easily change force or Four of these ranges use on-chip sense resistors; one high current measure conditions, DAC levels, and selected current ranges. range up to ±80 mA is available per channel using off-chip sense The SDO (serial data output) pin allows the user to read back resistors. Currents in excess of ±80 mA require an external ampli- information for diagnostic purposes. fier. Low capacitance DUT connections (FOHx and EXTFOHx) ensure that the device is suited to relayless test systems. Rev. F | Page 4 of 64 Document Outline Features Applications Functional Block Diagram Revision History General Description Specifications Timing Characteristics Circuit and Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Force Amplifier Comparators Clamps Current Range Selection High Current Ranges Measure Current Gains VMID Voltage Choosing Power Supply Rails Measure Output (MEASOUTx Pins) Device Under Test Ground (DUTGND) Guard Amplifier Compensation Capacitors System Force and Sense Switches Temperature Sensor DAC Levels Offset DAC Gain and Offset Registers Cached X2 Registers Gain and Offset Registers for the FIN DAC Gain and Offset Registers for the Comparator DACs Gain and Offset Registers for the Clamp DACs Reference Voltage (VREF) Reference Selection Reference Selection Example Calibration Reducing Zero-Scale Error Reducing Gain Error Calibration Example Additional Calibration System Level Calibration Circuit Operation Force Voltage (FV) Mode Force Current (FI) Mode Serial Interface SPI Interface LVDS Interface Serial Interface Write Mode RESETB Function BUSYB and LOADB Functions Register Update Rates Register Selection Readback Control, RD/WRB PMU Address Bits: PMU3, PMU2, PMU1, PMU0 NOP (No Operation) Reserved Commands Write System Control Register Write PMU Register Write DAC Register DAC Addressing Read Registers Readback of System Control Register Readback of PMU Register Readback of Comparator Status Register Readback of Alarm Status Register Readback of DAC Register Applications Information Power-On Default Setting Up the Device on Power-On Changing Modes Required External Components Power Supply Decoupling Power Supply Sequencing Typical Application for the AD5522 Outline Dimensions Ordering Guide
