Datasheet AD5560 (Analog Devices) - 2

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AD5560 Data Sheet TABLE OF CONTENTS
Features .. 1 Adjusting the Autocompensation Mode ... 39 Applications ... 1 Dealing with Parallel Load Capacitors .. 39 General Description ... 1 DAC Levels .. 39 Revision History ... 3 Force and Comparator DACs ... 39 Functional Block Diagram .. 4 Clamp DACs ... 39 Specifications ... 5 OSD DAC .. 40 Timing Characteristics .. 13 DUTGND DAC .. 40 Timing Diagrams .. 13 Offset DAC .. 40 Absolute Maximum Ratings .. 15 Offset and Gain Registers .. 40 ESD Caution .. 15 Reference Selection .. 41 Pin Configurations and Function Descriptions ... 16 Calibration... 41 Typical Performance Characteristics ... 20 Additional Calibration ... 41 Terminology .. 28 System Level Calibration ... 41 Theory of Operation .. 29 Choosing AVDD/AVSS Power Supply Rails ... 42 Force Amplifier ... 29 Choosing HCAVSSx and HCAVDDx Supply Rails ... 42 DAC Reference Voltage (VREF) ... 29 Power Dissipation... 42 Open-Sense Detect (OSD) Alarm and Clamp ... 29 Package Composition and Maximum Vertical Force .. 43 Device Under Test Ground (DUTGND)... 29 Slew Rate Control ... 43 GPO .. 29 Serial Interface .. 45 Comparators .. 30 SPI Interface .. 45 Current Clamps .. 30 SPI Write Mode .. 45 Short-Circuit Protection .. 30 SDO Output .. 45 Guard Amplifier ... 30 RESET Function ... 45 Compensation Capacitors ... 30 BUSY Function ... 45 Current Range Selection .. 31 LOAD Function .. 45 High Current Ranges ... 31 Register Update Rates .. 46 Ideal Sequence for Gang Mode ... 32 Control Registers .. 47 Compensation for Gang Mode ... 32 DPS and DAC Addressing .. 47 System Force/Sense Switches .. 32 Readback Mode .. 58 Die Temperature Sensor and Thermal Shutdown.. 33 DAC Readback.. 58 Measure Output (MEASOUT) ... 33 Power-On Default .. 58 VMID Voltage .. 33 Using the HCAVDDx and HCAVSSx Supplies .. 60 Force Amplifier Stability.. 36 Power Supply Sequencing ... 60 Poles and Zeros in a Typical System .. 37 Required External Components ... 61 Minimizing the Number of External Compensation Power Supply Decoupling ... 62 Components .. 37 Applications Information .. 63 Extra Poles and Zeros in the AD5560 .. 37 Thermal Considerations .. 63 Compensation Strategies ... 38 Temperature Contour Map on the Top of the Package ... 64 Optimizing Performance for a Known Capacitor Using Autocompensation Mode .. 38 Outline Dimensions ... 65 Ordering Guide .. 66 Rev. E | Page 2 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE