Datasheet AD5560 (Analog Devices) - 4

AD5560 Data Sheet FUNCTIONAL BLOCK DIAGRAM 1
001 07779-
E S N E S EXT R 2 ESNESEXTR DUT UT F4 1 E 2 ND O E1 E2 H L C SE H F4 G C C IN SI SI SI R_ R R R O C E T O O C O O SEN EA F EA EA ND DUT VE_ T T F F F0 M M M SE _ G A RCE S AS C F0 UARD/ O Y SL M C EXT EXT SYS_ SYS_ F EXT EXT EXT SEN G S DUT A A 6 .2 1 1 1 UX 8 9 SW Ω M 500m O ± SW T ± SW SW 10k P O 8 T U 1 P U SW a 5 b 5 7 SW 1 2x A A A SW µ A µ A µ SW DD 5m V 5 25m 2. 250 25 5560 A 7 D HC 3 4 5 1 1 1 A SW 2x SW SW SW P SS UARD V 20Ω 200Ω 2kΩ G AM A 20kΩ 100kΩ HC 4 E S 1x N SW E E E SS S CK R NS V O NS M E E A ARM SE AL BL HC AL L ND S SEN ND S UARD 1x G G G KE T ARM K BI AND DD AL V DUT DUT A INHI HC SE CT E pF PEN T 8 O SEN DE + – + – + – + – Ω M 100kΩ : 200Ω P C3 O 1 R T C 25kΩ GS D DAC C2C 6kΩ + – + 0 – E 2 D 0 1 DE O C1 1 × × T × OS DAC C V L RANG V V /V TE OR 16 A/ A/ A/ A A ID CO GE R I µ RO A E E E C0 µ µ R DBACK 1 2 T S S C Ω m E L 40 80 300 900µ g E E NT NT N E O ND N F M C C E E EW V F R R DAC M CE S 16 E .6 L I S CO O O AG V R SL A F F V : 500Ω T T Z O 1 OC X X C F R T L E E 2 E B R V SW A C 1 SW A B A B N P L W M M AND A 3 L EM R AL AL N RM DO P P SW CL RO FI IE T SO HE TM AM T HUT NT D S N/ R4 SEN E AD CL H L O CO H N CL L CP H L IN W SET CP SET F F Y CL CL /W DO F F SET SET S O IT F F IT O R3 B F F B E BUS IT IT HUT DAC DAC IT ND 16- 16- A B O B O B SET F S NS ACE C DAC DAC DAC L E IC IC B F DG 16- 16- 16- F A T T O S 16 16 ER OS SYN RM SE SE ND S T SE NO SE N 16 16 16 G G G HE GN I E E DI CC R2 T AG R R SEN SEN IA S G G G 2 2 ISEN VSEN K T DUT D DI SPI DV E E E × × L K R R R 2 2 2 IA × × H 2 × CL IN 0. CL S UX × C SER A R1 M 1/ ×8 ×8 AND GA × DO DD IT S V 1 1 1 T D B G G G G G G A × × × E G H DAC E E E E E 16- R R G G G CL 1 R 1 R E G G G G R G G FFS × × E E E E M C RE M C RE P E ND R R R O ND 6 1 R 1 R 1 R 1 × M C RE × M C RE × M C RE AG RAM AG PO SW G 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 SSV N A -O ER ESET ESET W R R PO K O L EF ND AD H/ O UT G O O CP O VR F RCL L CP CP AS RE E INH/ _ M HW
Figure 1. Rev. E | Page 4 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE