Datasheet AD5749 (Analog Devices) - 6

AD5749 Data Sheet Timing Diagrams t1 SCLK 1 2 16 t3 t2 t6 t4 t5 SYNC t8 t7 SDIN D15 D0 CLEAR t10 t9 IOUT RESET
2
t13
00 3- 92 08 Figure 2. Write Mode Timing Diagram
SCLK SYNC t11 A2 SDIN A1 A0 R = 1 0 R3 R2 R1 R0 CLRSEL OUTEN CLEAR RSET RESET 0 0 t12 SDO X X X X X R3 R2 R1 R0 CLRSEL OUTEN RSET PEC OVER IOUT X ERROR TEMP FAULT
-003 08923 Figure 3. Readback Mode Timing Diagram Rev. E | Page 6 of 28 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY TIMING CHARACTERISTICS Timing Diagrams ESD CAUTION SOFTWARE MODE CURRENT OUTPUT ARCHITECTURE DRIVING INDUCTIVE LOADS POWER-ON STATE OF THE AD5749 DEFAULT REGISTERS AT POWER-ON RESET FUNCTION OUTEN SOFTWARE CONTROL Input Shift Register Status Bit Read Operation HARDWARE CONTROL TRANSFER FUNCTION OUTPUT FAULT ALERT—SOFTWARE MODE OUTPUT FAULT ALERT—HARDWARE MODE ASYNCHRONOUS CLEAR (CLEAR) EXTERNAL CURRENT SETTING RESISTOR PROGRAMMABLE OVERRANGE MODES PACKET ERROR CHECKING TRANSIENT VOLTAGE PROTECTION THERMAL CONSIDERATIONS LAYOUT GUIDELINES GALVANICALLY ISOLATED INTERFACE MICROPROCESSOR INTERFACING ORDERING GUIDE