Datasheet ADSP-BF700, 701, 702, 703, 704, 705, 706, 707 (Analog Devices)

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Blackfin+ Core Embedded Processor ADSP-BF700/ 701 /702 /703 /704/ 705/ 706/ 707 FEATURES MEMORY Blackfin+ core with up to 400 MHz performance 136 kB L1 SRAM with multi-parity-bit protection
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Dual 16-bit or single 32-bit MAC support per cycle (64 kB instruction, 64 kB data, 8 kB scratchpad) 16-bit complex MAC and many other instruction set Large on-chip L2 SRAM with ECC protection enhancements 256 kB, 512 kB, 1 MB variants Instruction set compatible with previous Blackfin products On-chip L2 ROM (512 kB) Low-cost packaging L3 interface (CSP_BGA only) optimized for lowest system 88-Lead LFCSP_VQ (QFN) package (12 mm × 12 mm),
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power, providing 16-bit interface to DDR2 or LPDDR DRAM RoHS compliant devices (up to 200 MHz) 184-Ball CSP_BGA package (12 mm × 12 mm × 0.8 mm Security and one-time-programmable memory pitch), RoHS compliant Crypto hardware accelerators Low system power with < 100 mW core domain power at Fast secure boot for IP protection 400 MHz (< 0.25 mW/MHz) at 25°C TJUNCTION memDMA encryption/decryption for fast run-time security AEC-Q100 qualified for automotive applications PERIPHERALS FEATURES See Figure 1 , Processor Block Diagram and Table 1, Pr ocessor
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Comparison SYSTEM CONTROL BLOCKS PERIPHERALS 1× TWI EMULATOR PLL & POWER FAULT EVENT WATCHDOG TEST & CONTROL MANAGEMENT MANAGEMENT CONTROL 8× TIMER 1× COUNTER 2× CAN L2 MEMORY UP TO 2× UART
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1M BYTE SRAM 512K BYTE ROM ECC-PROTECTED SPI HOST PORT (& DMA MEMORY 136K BYTE PARITY BIT PROTECTED PROTECTION) 2x QUAD SPI GPIO L1 SRAM INSTRUCTION/DATA 1x DUAL SPI 2× SPORT 1× MSI SYSTEM FABRIC (SD/SDIO) 1× PPI EXTERNAL ANALOG BUS HARDWARE SUB STATIC MEMORY INTERFACES FUNCTIONS SYSTEM CONTROLLER MEMORY OTP SYSTEM PROTECTION PROTECTION MEMORY 3× MDMA 2× CRC STREAMS CRYPTO ENGINE (SECURITY) HADC DYNAMIC MEMORY CONTROLLER 1× RTC LPDDR 1× USB 2.0 HS OTG 16 DDR2
Figure 1. Processor Block Diagram Blackfin, Blackfin+, and the Blackfin logo are registered trademarks of Analog Devices, Inc.
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Document Outline Blackfin+ Core Embedded Processor Features Peripherals Features Memory Table of Contents Revision History General Description Blackfin+ Processor Core Instruction Set Description Processor Infrastructure DMA Controllers Event Handling Trigger Routing Unit (TRU) General-Purpose I/O (GPIO) Pin Interrupts Pin Multiplexing Memory Architecture Internal (Core-Accessible) Memory OTP Memory Static Memory Controller (SMC) Dynamic Memory Controller (DMC) I/O Memory Space Booting Security Features Security Features Disclaimer Processor Safety Features Multi-Parity-Bit-Protected L1 Memories ECC-Protected L2 Memories CRC-Protected Memories Memory Protection System Protection Watchpoint Protection Watchdog Bandwidth Monitor Signal Watchdogs Up/Down Count Mismatch Detection Fault Management Additional Processor Peripherals Timers Serial Ports (SPORTs) General-Purpose Counters Parallel Peripheral Interface (PPI) Serial Peripheral Interface (SPI) Ports SPI Host Port (SPIHP) UART Ports 2-Wire Controller Interface (TWI) Mobile Storage Interface (MSI) Controller Area Network (CAN) USB 2.0 On-the-Go Dual-Role Device Controller Housekeeping ADC (HADC) System Crossbars (SCB) Power and Clock Management System Crystal Oscillator and USB Crystal Oscillator Real-Time Clock Clock Generation Clock Out/External Clock Power Management Reset Control Unit Voltage Regulation System Debug System Watchpoint Unit Debug Access Port Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits ADSP-BF706 EZ-KIT Mini Blackfin Low Power Imaging Platform (BLIP) Software Add-Ins for CrossCore Embedded Studio Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-BF70x Detailed Signal Descriptions 184-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 184-Ball CSP_BGA 12 mm × 12 mm 88-Lead LFCSP (QFN) Signal Descriptions GPIO Multiplexing for 12 mm × 12 mm 88-Lead LFCSP (QFN) ADSP-BF70x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications Absolute Maximum Ratings ESD Sensitivity Timing Specifications Clock and Reset Timing Power-Up Reset Timing Asynchronous Read SMC Read Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Read Asynchronous Page Mode Read Asynchronous Write SMC Write Cycle Timing With Reference to SYS_CLKOUT Asynchronous Flash Write All Accesses DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing General-Purpose I/O Port Timing (GPIO) Timer Cycle Timing Up/Down Counter/Rotary Encoder Timing Debug Interface (JTAG Emulation Port) Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Slave Timing Serial Peripheral Interface (SPI) Port—Open Drain Mode (ODM) Timing Serial Peripheral Interface (SPI) Port—SPI_RDY Timing Enhanced Parallel Peripheral Interface Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) Mobile Storage Interface (MSI) Controller Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-BF70x 184-Ball CSP_BGA Ball Assignments (Numerical by Ball Number) ADSP-BF70x 12 mm × 12 mm 88-Lead LFCSP (QFN) Lead Assignments (Numerical by Lead Number) Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide