Datasheet STD30NF06LAG (STMicroelectronics) - 5

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STD30NF06LAG Electrical characteristics Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time - 30 - VDD = 30 V, ID = 18 A, RG = 4.7 Ω, tr Rise time V - 105 - GS = 4.5 V ns (see Figure 14: "Test circuit for gate td(off) Turn-off delay time - 65 - charge behavior") tf Fall time - 25 -
Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit
ISD Source-drain current - 35 A Source-drain current I (1) SDM - 140 A (pulsed) V (2) SD Forward on voltage VGS = 0 V, ISD = 35 A - 1.5 V Reverse recovery trr - 70 ns time I SD = 35 A, di/dt = 100 A/µs, Reverse recovery VDD = 15 V, TJ = 150 °C Qrr - 140 nC charge (see Figure 18: "Switching time waveform") Reverse recovery IRRM - 4 A current
Notes:
(1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID029664 Rev 2 5/15