Datasheet ISOSD61 (STMicroelectronics) - 7

ISOSD61 Device specifications Parameter Symbol Min. Typ. Max. Units Test conditions
Signal-to-noise ratio SNR 86 dB Signal-to-(noise + distortion) ratio SNDR 80 dB Effective number of bits ENOB 13 bits Spurious free dynamic Range SFDR 83 dB Total harmonic distortion THD -83 dB Transient Pulse repetition frequency Common-mode transient immunity CMTI 25 30 kV/µs up to 100 KHz
POWER SUPPLY
35 mA @ 25 MHz VDDISO supply current IDDISO 30 mA @ 10 MHz VDD = 5 V, 13 mA fMCLKIN = 25 MHz VDD = 5 V, 11 mA fMCLKIN = 10 MHz VDD supply current IDD VDD = 3.3 V, 12.5 mA fMCLKIN = 25 MHz VDD = 3.3 V, 10.5 mA fMCLKIN = 10 MHz 1. Guaranteed by characterization
Table 8. Timing specifications Symbo Parameter Min. Typ. Max. Units Test conditions l
Modulator clock input frequency fCK 5 25 MHz Clock duty cycle 48% to 52% Data delay after rising edge of CK tD 5 20 ns CL = 15 pF
Figure 4. Timing sequence diagram
MCLK 1 2 3 4 MDAT t MCLK period D The data is provided to the MDAT output 2 clock cycles after the effective sampling instant.
DS13605
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Rev 3 page 7/23
Document Outline Cover image Product status link / summary Features Application Description 1 Device overview 2 Pin description 3 Device specifications 4 Terminology 5 Theory of operation 6 Package description 7 Ordering information Revision history Contents List of tables List of figures