EPC21603 – 40 V, 10 A eToF Laser Driver IC –PRELIMINARYApplication Information Layout and decoupling: Minimizing inductance in both power and gate drive loops is critical. The power loop is primary, and gate drive loop secondary. Short, wide traces are required, and returning in the second layer, using a thin dielectric wil cancel much of the inductance. Using multiple ceramic capacitors in parallel will reduce stray inductance and impedance in the power loop. Use high quality NPO or COG capacitors for both power and gate drive. This will increase effective capacitance as capacitors with lower quality materials will lose much more capacitance with voltage. Recommended layout is shown below. Component recommendations for power and gate drive decoupling capacitors are shown in the demonstration board quick start guide. Turn off current is limited by the energy of the power loop stray inductance transferring to the COSS of the power FET of the laser driver. EOSS versus VDS curve is in the datasheet. Cathode to drain connection on second conductor layer. Start up: VDD should be applied before the laser voltage. For applications where the laser voltage is below 10 V, it may take a few pulses before the pulse width stabilizes. For correct measurement, it may be necessary to ignore the first few pulses. Subject to Change without Notice www.epc-co.com COPYRIGHT 2021 Page 5
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