Datasheet L6981 (STMicroelectronics) - 10

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L6981 Undervoltage lockout Figure 6. Soft-start phase with IOUT = 1.25 A 6.3 Undervoltage lockout
The device implements the undervoltage lockout (UVLO) continuously sensing the voltage on the VCC pin, if the UVLO lasts more than 10 μs, the internal logic resets the device by turning off both LS and HS. After the reset, if the EN pin is still high, the device repeats the soft-start procedure.
6.4 Light-load operation
The L6981 implements two different light-load strategies: 1. Low consumption mode (LCM). 2. Low noise mode (LNM). Please refer to Table 11 to select the part number with the preferred light-load strategy.
6.4.1 Low consumption mode (LCM)
The LCM maximizes the efficiency at light-load. When the switch peak current request is lower than the ISKIP threshold (please refer to Electrical characteristics table), the device regulates VOUT by the skip threshold. The minimum voltage is given by: R V PH + RPL OUT,  LCM =  VFB,  LCM ∙ R (1) PL Where VFB, LCM is 1.8% (typ.) higher than VFB. The device interrupts the switching activities when two conditions happen together: 1. The peak inductor current required is lower than ISKIP. 2. The voltage on the FB pin is higher than VFB, LCM.
DS13554
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Rev 1 page 10/49
Document Outline 1 Diagram 2 Pin configuration 3 Typical application circuit 4 Absolute maximum ratings 5 Electrical characteristics 6 Functional description 6.1 Enable 6.2 Soft-start 6.3 Undervoltage lockout 6.4 Light-load operation 6.4.1 Low consumption mode (LCM) 6.4.2 Low noise mode (LNM) 6.4.3 Efficiency for Low consumption mode and Low noise mode part number 6.4.4 Load regulation for low consumption mode and low noise mode part number 6.5 Overvoltage protection 6.5.1 Low consumption mode part number 6.5.2 Low noise mode part number 6.6 Overcurrent protection 6.7 Thermal shutdown 7 Closing the loop 7.1 GCO(s) control to output transfer function 7.2 Error amplifier compensation network 7.3 Voltage divider 8 Design of the power components 8.1 Programmable power up threshold 8.2 External synchronization (only available for Low Noise Mode) 8.3 Output voltage adjustment 8.4 Design of the power components 8.4.1 Input capacitor selection 8.4.2 Inductor selection 8.4.3 Output capacitor selection 9 Application board 10 Efficiency curves 11 Thermal dissipation 12 Package information 12.1 SO 8L package information 13 Ordering information Revision history