Datasheet PMN50XP (NXP) - 7

NXP Semiconductors PMN50XP P-channel TrenchMOS extremely low level FET
03aq09 -5 V I GS D = -4.7 A (V) Tj = 25 °C -4 VDS = -10 V VDS ID -3 VGS(pl) -2 VGS(th) V -1 GS QGS1 QGS2 Q Q GS GD 0 QG(tot) 0 4 8 12 QG (nC) 003aaa508 I = í4.7 A; T = 25 °C; V = í10 V D j DS
Fig 9. Gate-source voltage as a function of gate Fig 10. Gate charge waveform definitions charge; typical values
001aae335 104 C (pF) 103 Ciss Coss 102 Crss 10 −10−1 −1 −102 −10 VDS (V) V = 0 V ; f = 1 M H z GS
Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
PMN50XP_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 October 2007 7 of 11
Document Outline 1. Product profile 1.1 General description 1.2 Features 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Limiting values 5. Thermal characteristics 6. Characteristics 7. Package outline 8. Revision history 9. Legal information 9.1 Data sheet status 9.2 Definitions 9.3 Disclaimers 9.4 Trademarks 10. Contact information 11. Contents