Datasheet 74AHCU04 (Nexperia) - 2

Nexperia 74AHCU04 Hex unbuffered inverter 4. Functional diagram
1 1 2 1 1A 1Y 2 1 3 4 3 2A 2Y 4 1 5 6 5 3A 3Y 6 1 9 8 9 4A 4Y 8 11 5A 5Y 10 1 11 10 13 6A 6Y 12 1 13 12 A Y mna342 mna343 mna045
Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one inverter) 5. Pinning information 5.1. Pinning
C terminal 1 1A V C index area 1 14 1Y 2 13 6A 2A 3 12 6Y 2Y 4
04
11 5A 3A 5 10 5Y 1A 1 14 V GND(1) CC 1Y 2 13 6A 3Y 6 9 4A 7 8 2A 3 12 6Y D 2Y 4
04
11 5A N 4Y 001aac442 G 3A 5 10 5Y Transparent top view 3Y 6 9 4A (1) This is not a ground pin. There is no electrical or GND 7 8 4Y mechanical requirement to solder the pad. In case 001aac441 soldered, the solder land should remain floating or
Fig. 4. Pin configuration SOT108-1 (SO14) and
connected to GND.
SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description
1A, 2A, 3A, 4A, 5A, 6A 1, 3, 5, 9, 11, 13 data input 1Y, 2Y, 3Y, 4Y, 5Y, 6Y 2, 4, 6, 8, 10, 12 data output GND 7 ground (0 V) VCC 14 supply voltage 74AHCU04 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2020. Al rights reserved
Product data sheet Rev. 5 — 18 May 2020 2 / 14
Document Outline 1. General description 2. Features and benefits 3. Ordering information 4. Functional diagram 5. Pinning information 5.1. Pinning 5.2. Pin description 6. Functional description 7. Limiting values 8. Recommended operating conditions 9. Static characteristics 10. Dynamic characteristics 10.1. Waveforms 11. Typical transfer characteristics 12. Application information 13. Package outline 14. Abbreviations 15. Revision history 16. Legal information Contents