LTC3337 APPLICATIONS INFORMATION This cycle can also continue indefinitely. Once all chips condition. After a STOP condition, all pending data is cop- on the bus have been addressed and sent valid data, a ied to the command registers for immediate effect. global STOP can be sent and the LTC3337 will immedi- When the contents of the sub-address pointer register ately update all of its command registers with the most point to the writable and readable register B, the data recent pending data that it had previously received. returned in a bus read operation is data at that location, not the pending command data from the previous write BUS READ OPERATION operation. After a STOP condition, all pending data is cop- Only one sub-addressed data register is accessible ied to the command registers for immediate effect and a during each bus read operation. The data returned by subsequent read operation can read the effect. the LTC3337 is from the data register pointed to by the When the contents of the sub-address pointer register contents of the sub-address pointer register. The pointer point to the read-only registers (C, D, E, F, G), the data register contents are determined by the previous bus write returned is a snapshot of the state of the LTC3337 at operation. In preparation for a bus read operation, it may a particular instant in time. If no interrupt requests are be advantageous for a bus master to prematurely termi- pending, the status data is sampled when the LTC3337 nate a write transaction with a STOP or repeat START acknowledges its read address, just before the LTC3337 condition. The last transmitted byte then represents a begins data transmission during a bus read operation. If pointer to the register of interest for the subsequent bus the read address is acknowledged during an ADC con- read operation. version or IPEAK pulse the status data reported is the The bus master reads status data from the LTC3337 one from the previous ADC conversion or end of the last with a START or repeat START condition followed by the IPEAK pulse. LTC3337 read address. If the read address matches that When an alarm/fault occurs, the IRQ pin is driven low and of the LTC3337, the LTC3337 returns an acknowledge. data is latched in bits C[3:0] of status register C at that Following the acknowledgement of its read address, the moment. Any subsequent read operation from register C LTC3337 returns one bit of status information for each will return these frozen C[3:0] bits to facilitate determi- of the next eight clock cycles from the register selected nation of the cause of the interrupt request. by the sub-address pointer (LSB first data byte). The After the bus master clears the LTC3337 interrupt request, SDA line stays high for 1-clock cycle after the first 8 bits bits C[3:0] of the status latches are cleared. Bus read and after LTC3337 returns the second data byte (MSB). operations will then again return either a snapshot of the Additional clock cycles from the master after the 2 data data at the time of the read address acknowledge, after an bytes have been read will leave the SDA line high. The ADC conversion, after the IPEAK pulse, or at the time of the LTC3337 will never acknowledge any bytes during a bus next interrupt assertion, whichever comes first. read operation except for its read address. To read a different register, a write transaction must be PC BOARD LAYOUT initiated with a START or repeat START followed by the Despite its ultralow current operation, all high impedance LTC3337 write address and sub-address pointer byte nodes of the LTC3337 are inside the IC, and therefore, before the read transaction may be repeated. no special layout is needed. The positive terminals of the When the contents of the sub-address pointer register input and output capacitors should be connected as close point to write-only registers (A, H), the data returned in as possible to the BAT_IN and BAT_OUT pins, respec- a bus read operation is the pending command data at tively, and the negative terminals as close as possible to that location if it had been modified since the last STOP the GND pin. Rev. 0 For more information www.analog.com 19 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Electrical Characteristics Timing Diagram Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Applications Related Parts