Datasheet ALED6000 (STMicroelectronics) - 5

ALED6000 Maximum ratings # Pin Description
A pull-down resistor to GND selects the 11 ILIM peak current limitation A PWM signal in this input pin implements the LED PWM current 12 DIM dimming. It is pulled-down by internal 2 µA current 13 LX Switching node 14 LX Switching node Connect an external capacitor (100 nF typ.) between BOOT and LX pins. The 15 BOOT gate charge required to drive the internal n-DMOS is recovered by an internal regulator during the off-time 16 GND Signal GND Exposed pad must be connected to -- E.P. GND plane
3.3 Maximum ratings
Stressing the device above the rating listed in may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability.
Table 2. Absolute maximum ratings Symbol Description Min. Max. Unit
VIN -0.3 61 V VCC -0.3 61 V VBOOT - GND -0.3 65 V BOOT VBOOT – VLX -0.3 4 V VBIAS -0.3 VCC V EN -0.3 VCC V DIM -0.3 VCC V LX -0.3 VIN+0.3 V SYNCH -0.3 5.5 V SS -0.3 3.6 V FSW -0.3 3.6 V COMP -0.3 3.6 V ILIM -0.3 3.6 V FB -0.3 3.6 V T Operating temperature J -40 150 °C range T Storage temperature STG -65 150 °C range T Lead Temperature LEAD 260 °C (soldering 10 s) IHS High-side RMS current 3 A
DS13018
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Document Outline Cover image Features Applications Description 1 Application schematic 2 Block diagram 3 Pin settings 3.1 Pin connection 3.2 Pin description 3.3 Maximum ratings 3.4 Thermal data 3.5 ESD protection 4 Electrical characteristics 5 Functional description 5.1 Oscillator and synchronization 5.2 Soft-start 5.3 Digital dimming 5.4 Error amplifier and light-load management 5.5 Low VIN operation 5.6 Overcurrent protection 5.7 Overtemperature protection 6 Application information 6.1 Input capacitor selection 6.2 Output capacitor and inductor selection 6.3 Compensation strategy 6.4 Thermal considerations 6.5 Layout considerations 7 Demonstration board 8 Application notes – alternative topologies 8.1 Inverting buck-boost 8.2 Positive buck-boost 8.3 Floating boost 8.4 Compensation strategy for alternative topologies 9 Package information 9.1 HTSSOP16 package information Revision history