Fast, Low-Voltage, Dual 4 Ω SPDTCMOS Analog SwitchesMAX4635/MAX4636 MAX4635/MAX4636 tr < 5ns V+ VIH + 0.5V tf < 5ns 50% LOGIC V+ 0 INPUT NC_ or NO_ V V IN OUT COM_ tOFF NO_ or NC_ R CL V L OUT IN_ 0.9 ✕ V0UT 0.9 ✕ VOUT SWITCH 0 OUTPUT LOGIC GND tON INPUT LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES C THAT HAVE THE OPPOSITE LOGIC SENSE. L INCLUDES FIXTURE AND STRAY CAPACITANCE. Figure 1a. Switching Time tr < 5ns tf < 5ns MAX4635/MAX4636 V+ VIH + 0.5V LOGIC 50% V+ INPUT 0 NC_ or NO_ V V IN OUT COM_ NO_ or NC_ RL CL IN_ LOGIC GND INPUT V 0.9 ✕ V OUT OUT tD CL INCLUDES FIXTURE AND STRAY CAPACITANCE. Figure 1b. Break-Before-Make Interval MAX4635/MAX4636 V+ ∆VOUT V+ VOUT RGEN NC_ COM_ VOUT OR NO_ IN C OFF OFF L V ON GEN GND IN ON OFF OFF IN VINL TO VINH Q = (∆VOUT)(CL) IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. Figure 2. Charge Injection _______________________________________________________________________________________7
