Datasheet NC7SV57, NC7SV58 (ON Semiconductor) - 3

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NC7SV57, NC7SV58 Logic Configurations NC7SV57 Figure 2. 2−Input AND Gate Figure 3. 2−Input NAND with Inverted A Input Figure 4. 2−Input NAND with Inverted B Input Figure 5. 2−Input NOR Gate Figure 6. 2−Input XNOR Gate
NOTE: Figure 2 through Figure 6 show the logical functions that can be implemented using the NC7SV57. The diagrams show the DeMorgan’s equivalent logic duals for a given 2−input function. Next to the logical implementation is the board level physical implementation of how the pins of the function should be connected.
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