Datasheet MJ14001, MJ14002, MJ14003 (ON Semiconductor)

MJ14001 (PNP), MJ14002* (NPN), MJ14003* (PNP)
*Preferred Devices
High−Current Complementary Silicon Power Transistors Designed for use in high−power amplifier and switching circuit
http://onsemi.com
applications.
Features 60 AMPERE
• High Current Capability − IC Continuous = 60 Amperes
COMPLEMENTARY SILICON
• DC Current Gain − hFE = 15−100 @ IC = 50 Adc •
POWER TRANSISTORS
Low Collector−Emitter Saturation Voltage −VCE(sat) = 2.5 Vdc (Max) @ I
60−80 VOLTS, 300 WATTS
C = 50 Adc • Pb−Free Packages are Available*
MAXIMUM RATINGS
(T
MARKING
J = 25°C unless otherwise noted)
DIAGRAM Rating Symbol Value Unit
Collector−Emitter Voltage MJ14001 VCEO 60 Vdc MJ14002/03 80 Collector−Base Voltage MJ14001 VCBO 60 Vdc MJ14002/03 80 MJ1400xG Emitter−Base Voltage VEBO 5.0 Vdc AYYWW MEX Collector Current − Continuous IC 60 Adc Base Current − Continuous IB 15 Adc
TO−204 (TO−3)
Emitter Current − Continuous I
CASE 197A
E 75 Adc
STYLE 1
Total Power Dissipation @ TC = 25°C PD 300 W Derate Above 25°C 1.71 W/°C MJ1400x = Device Code Operating and Storage Junction TJ, Tstg −65 to +200 °C xx = 1, 2, or 3 Temperature Range G = Pb−Free Package Maximum ratings are those values beyond which device damage can occur. A = Location Code Maximum ratings applied to the device are individual stress limit values (not YY = Year normal operating conditions) and are not valid simultaneously. If these limits are WW = Work Week exceeded, device functional operation is not implied, damage may occur and MEX = Country of Orgin reliability may be affected. 360
ORDERING INFORMATION
330
Device Package Shipping
ATTS) MJ14001 TO−3 100 Units/Tray (W 270 MJ14001G TO−3 100 Units/Tray ATION 210 (Pb−Free) MJ14002 TO−3 100 Units/Tray 150 MJ14002G TO−3 100 Units/Tray (Pb−Free) 90 , POWER DISSIP MJ14003 TO−3 100 Units/Tray P D 30 MJ14003G TO−3 100 Units/Tray 0 (Pb−Free) 0 40 80 120 160 200 240 TC, CASE TEMPERATURE (°C)
Preferred
devices are recommended choices for future use
Figure 1. Power Derating
and best overall value. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
December, 2005 − Rev. 6 MJ14001/D