Datasheet ADGS1412 (Analog Devices) - 10

ADGS1412 Data Sheet Timing Diagrams t1 SCLK t2 t t t7 4 3 CS t t 6 5 SDI R/W A6 A5 D2 D1 D0 t t 9 10 SDO 0 0 1 D2 D1 D0
002
t8
14960- Figure 2. Address Mode Timing Diagram
t1 SCLK t t 3 2 t4 t7 CS t t 6 5 SDI D7 D6 D0 D7 D6 D1 D0 INPUT BYTE FOR DEVICE N INPUT BYTE FOR DEVICE N + 1 t t10 9 SDO 0 0 0 D7 D6 D1 D0
003
ZERO BYTE INPUT BYTE FOR DEVICE N t8
14960- Figure 3. Daisy-Chain Timing Diagram
t11 CS SCLK
004
t13 t12
14960- Figure 4. SCLK/CS Timing Relationship Rev. B | Page 10 of 27 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±15 V DUAL SUPPLY ±5 V DUAL SUPPLY 12 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY THEORY OF OPERATION ADDRESS MODE ERROR DETECTION FEATURES Cyclic Redundancy Check (CRC) Error Detection SCLK Count Error Detection Invalid Read/Write Address Error CLEARING THE ERROR FLAGS REGISTER BURST MODE SOFTWARE RESET DAISY-CHAIN MODE POWER-ON RESET APPLICATIONS INFORMATION BREAK-BEFORE-MAKE SWITCHING DIGITAL INPUT BUFFERS POWER SUPPLY RAILS POWER SUPPLY RECOMMENDATIONS REGISTER SUMMARY REGISTER DETAILS SWITCH DATA REGISTER ERROR CONFIGURATION REGISTER ERROR FLAGS REGISTER BURST ENABLE REGISTER SOFTWARE RESET REGISTER OUTLINE DIMENSIONS ORDERING GUIDE