Datasheet ADG1611, ADG1612, ADG1613 (Analog Devices) - 9

Data Sheet ADG1611/ADG1612/ADG1613 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS IN2 IN1 D1 D2 IN1 1 16 IN2 16 15 14 13 D1 2 15 D2 S1 3 14 S2 ADG1611/ S1 1 12 S2 ADG1612/ ADG1611/ V 4 SS 13 VDD ADG1613 V 2 SS ADG1612/ 11 VDD ADG1613 GND 5 TOP VIEW 12 NIC GND 3 10 NIC TOP VIEW (Not to Scale) (Not to Scale) S4 6 11 S3 S4 4 9 S3 D4 7 10 D3 5 6 7 8 IN4 8 9 IN3 D4 IN4 IN3 D3 NOTES
002 003
NOTES 1. NIC = NOT INTERNALLY CONNECTED. 1. NIC = NOT INTERNALLY CONNECTED. 2. EXPOSED PAD TIED TO SUBSTRATE, V
07981-
SS.
07981- Figure 4. 16-Lead TSSOP Pin Configuration Figure 5. 16-Lead LFCSP Pin Configuration
Table 7. Pin Function Descriptions Pin No. 16-Lead TSSOP 16-Lead LFCSP Mnemonic Description
1 15 IN1 Logic Control Input. 2 16 D1 Drain Terminal. This pin can be an input or output. 3 1 S1 Source Terminal. This pin can be an input or output. 4 2 VSS Most Negative Power Supply Potential. 5 3 GND Ground (0 V) Reference. 6 4 S4 Source Terminal. This pin can be an input or output. 7 5 D4 Drain Terminal. This pin can be an input or output. 8 6 IN4 Logic Control Input. 9 7 IN3 Logic Control Input. 10 8 D3 Drain Terminal. This pin can be an input or output. 11 9 S3 Source Terminal. This pin can be an input or output. 12 10 NIC Not Internally Connected. 13 11 VDD Most Positive Power Supply Potential. 14 12 S2 Source Terminal. This pin can be an input or output. 15 13 D2 Drain Terminal. This pin can be an input or output. 16 14 IN2 Logic Control Input. Not applicable 17 (EPAD) EP (EPAD) Exposed Pad. Tied to substrate, VSS.
Table 8. ADG1611/ ADG1612 T ruth Table ADG1611 IN x ADG1612 IN x Switch Condition
0 1 On 1 0 Off
Table 9. ADG1613 T ruth Table Logic (INx) Switch 1, Switch 4 Switch 2, Switch 3
0 Off On 1 On Off Rev. C | Page 9 of 16 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ±5 V DUAL SUPPLY 12 V SINGLE SUPPLY 5 V SINGLE SUPPLY 3.3 V SINGLE SUPPLY CONTINUOUS CURRENT PER CHANNEL, S OR D ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUITS TERMINOLOGY OUTLINE DIMENSIONS ORDERING GUIDE