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Datasheet ADG1206, ADG1207 (Analog Devices)

ПроизводительAnalog Devices
ОписаниеLow Capacitance, 16-and 8-Channel, ±15 V/+12 V iCMOS Multiplexers
Страниц / Страница20 / 1 — Low Capacitance, 16- and 8-Channel,. ±15 V/+12 V i. CMOS Multiplexers. …
ВерсияC
Формат / Размер файлаPDF / 386 Кб
Язык документаанглийский

Low Capacitance, 16- and 8-Channel,. ±15 V/+12 V i. CMOS Multiplexers. Data Sheet. ADG1206. /ADG1207. FEATURES

Datasheet ADG1206, ADG1207 Analog Devices, Версия: C

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Low Capacitance, 16- and 8-Channel, ±15 V/+12 V i CMOS Multiplexers Data Sheet ADG1206 /ADG1207 FEATURES FUNCTIONAL BLOCK DIAGRAMS <1 pC charge injection over full signal range ADG1206 ADG1207 1.5 pF off capacitance S1 S1A 33 V supply range DA 120 Ω on resistance S8A Fully specified at ±15 V/+12 V D 3 V logic-compatible inputs Rail-to-rail operation S1B DB Break-before-make switching action S16 S8B 28-lead TSSOP and 32-lead, 5 mm × 5 mm LFCSP 1-OF-16 1-OF-8 APPLICATIONS DECODER DECODER Audio and video routing
1 00 9-
Automatic test equipment A0 A1 A2 A3 EN A0 A1 A2 EN
11 06
Data acquisition systems
Figure 1.
Battery-powered systems Sample-and-hold systems Communication systems GENERAL DESCRIPTION
The ADG1206 and ADG1207 are monolithic iCMOS® analog The ultralow capacitance and exceptionally low charge injection multiplexers comprising sixteen single channels and eight of these multiplexers make them ideal solutions for data acquisition differential channels, respectively. The ADG1206 switches one and sample-and-hold applications, where low glitch and fast of sixteen inputs to a common output, as determined by the settling are required. Figure 2 shows that there is minimum 4-bit binary address lines A0, A1, A2, and A3. The ADG1207 charge injection over the entire signal range of the device. switches one of eight differential inputs to a common differential iCMOS construction also ensures ultralow power dissipation, output, as determined by the 3-bit binary address lines A0, A1, making the devices ideally suited for portable and battery- and A2. An EN input on both devices is used to enable or disable powered instruments. the device. When disabled, all channels are switched off. When
1.0
on, each channel conducts equally well in both directions and
MUX (SOURCE TO DRAIN) 0.9 TA = 25°C
has an input signal range that extends to the supplies.
0.8
The industrial CMOS (iCMOS) modular manufacturing
C) 0.7 (p
process combines high voltage, complementary metal-oxide
N IO 0.6
semiconductor (CMOS) and bipolar technologies. It enables the
CT VDD = +15V 0.5 V
development of a wide range of high performance analog ICs
JE N SS = –15V I E
capable of 33 V operation in a footprint that no other generation
0.4 RG
of high voltage devices has been able to achieve. Unlike analog
0.3 VDD = +12V CHA V
ICs using conventional CMOS processes, iCMOS components
SS = 0V 0.2
can tolerate high supply voltages while providing increased
0.1 VDD = +5V
performance, dramatically lower power consumption, and
VSS = –5V 0
reduced package size. 2
–15 –10 –5 0 5 10 15
-00
V
19
S (V)
61 0 Figure 2. Source-to-Drain Charge Injection vs. Source Voltage
Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAMS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DUAL SUPPLY SINGLE SUPPLY ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE