Datasheet ADG619-EP (Analog Devices) - 10

link to page 10 link to page 10
ADG619-EP OUTLINE DIMENSIONS 3.00 2.90 2.80 8 7 6 5 3.00 1.70 2.80 1.60 2.60 1.50 1 2 3 4 PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.30 1.15 0.90 1.45 MAX 0.22 MAX 0.95 MIN 0.08 MIN 0.60 0.15 MAX 8° 0.45 SEATING 0.05 MIN 4° 0.60 0.38 MAX PLANE BSC 0.30 0° 0.22 MIN A COMPLIANT TO JEDEC STANDARDS MO-178-BA 121608-
Figure 18. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters
ORDERING GUIDE Model
1
Temperature Range Package Description Package Option Branding2
ADG619SRJZ-EP-RL7 −55°C to +125°C 8-Lead Small Outline Transistor Package [SOT-23] RJ-8 S3V 1 Z =RoHS Compliant Part. 2 Branding on SOT-23 packages is limited to three characters due to space constraints Rev. 0 | Page 10 of 12 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications Dual Supply Single Supply Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Outline Dimensions Ordering Guide