Datasheet ADG528F (Analog Devices) - 5

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ADG528F TIMING DIAGRAMS
Figure 2 shows the timing sequence for latching the switch This input data is latched on the rising edge of WR. Figure 3 address and enable inputs. The latches are level sensitive; shows the reset pulse width, tRS, and the reset turnoff time, tOFF therefore, while WR is held low, the latches are transparent (RS). Note that all digital input signals rise and fall times are and the switches respond to the address and enable inputs. measured from 10% to 90% of 3 V. tR = tF = 20 ns.
3V WR 50% 50% 0V tW tS tH 3V 2V A0, A1, A2
2
EN
00
0.8V
5-
0V
65 09 Figure 2. Timing Sequence for Latching the Switch Address and Enable Inputs
3V RS 50% 50% 0V tRS tOFF (RS) VOUT 0.8VOUT SWITCH OUTPUT
3 00 5-
0V
65 09 Figure 3. Reset Pulse Width Rev. F | Page 5 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DUAL SUPPLY TRUTH TABLE TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION TEST CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE