Datasheet MAX9691, MAX9692, MAX9693 (Maxim) - 7

Single/Dual, Ultra-Fast, ECL-Output Comparators with Latch Enable MAX9691/MAX9692/MAX9693
The timing diagram (Figure 3) illustrates the series of sistors are similar in timing. The input signal must occur events that complete the compare function, under at time ts before the latch falling edge, and must be worst-case conditions. The top line of the diagram illus- maintained for time th after the edge to be acquired. trates two latch-enable pulses. Each pulse is high for After th, the output is no longer affected by the input sta- the compare function and low for the latch function. The tus until the latch is again strobed. A minimum latch first pulse demonstrates the compare function; part of pulse width of tpw(LE) is needed for the strobe opera- the input action takes place during the compare mode. tion, and the output transitions occur after a time tLE(±). The second pulse demonstrates a compare function The MAX9691/MAX9692/MAX9693 will not false trip interval during which there is no change in the input. (i.e., output invert) if one of the inputs is in the valid The leading edge of the input signal (illustrated as a common-mode range while the other input is outside large-amplitude, small-overdrive pulse) switches the the common-mode range. comparator after time interval tpd. Output Q and Q tran- COMPARE LATCH 50% ENABLE ts tpw(LE) LATCH th DIFFERENTIAL INPUT VIN VOLTAGE VOS VOD tpd tLE(+) Q 50% Q 50% Figure 3. Timing Diagram
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