Datasheet ADP3623, ADP3624, ADP3625, ADP3633, ADP3634, ADP3635 (Analog Devices) - 4

ADP3623/ADP3624/ADP3625/ADP3633/ADP3634/ADP3635 TIMING %*"(3".4 SD tdL_SD tdH_SD 90% OUTA,
002
OUTB 10%
08132- Figure 2. Shutdown Timing Diagram
INA, VIH VIL INB tD1 tRISE tD2 tFALL 90% 90% OUTA, OUTB 10% 10%
003 08132- Figure 3. Output Timing Diagram (Noninverting)
INA, VIL VIH INB tD1 tRISE tD2 tFALL 90% 90% OUTA, OUTB 10% 10%
003 08132- Figure 4. Output Timing Diagram (Inverting)
VUVLO_ON VUVLO_OFF VDD UVLO MODE NORMAL OPERATION UVLO MODE
005
OUTPUTS DISABLED OUTPUTS DISABLED
08132- Figure 5. UVLO Function Rev. A | Page 4 of 16 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuit Theory of Operation Input Drive Requirements (INA, AA, INB, AA, and SD) Low-Side Drivers (OUTA, OUTB) Shutdown (SD) Function Overtemperature Protections Supply Capacitor Selection PCB Layout Considerations Parallel Operation Thermal Considerations Design Example Outline Dimensions Ordering Guide