Low-Power, Adjustable Battery Monitors withHysteresis and Integrated µP ResetMAX6846–MAX6849 VDD VDD LTHIN MAX6847 MAX6848 LTHIN LTH DETECT LTH LBOL DETECT HTHIN R Q 5% HTHIN HYST S Q LBO LBO HTH TIMEOUT LBO TIMEOUT DETECT PERIOD PERIOD HTH LBOH DETECT 5% HYST 615mV 615mV VCC VCC VCC RESET RESET VTH TIMEOUT DETECT RESET V RESET TH PERIOD DETECT TIMEOUT PERIOD VCC 1.23V 1.23V MR Figure 1a. MAX6847 Functional Diagram Figure 1b. MAX6848 Functional Diagram Low-Battery Output rises above VHTH+. LBOL asserts when LTHIN drops The low-battery outputs are available in active-low below VLTH- and remains asserted for at least 150ms (LBO, LBOL, LBOH), open-drain configurations. The after LTHIN rises above VLTH+ (see Figure 3). For fast- low-battery outputs can be pulled to a voltage indepen- rising VDD input, the LBOL timeout period must com- dent of VCC or VDD, up to 5.5V. This allows the device plete before the LBOH timeout period begins. to monitor and operate from direct battery voltage while interfacing to higher voltage microprocessors. Reset Output The MAX6846–MAX6849 provide an active-low reset The MAX6846/MAX6847 single-output voltage monitors output (RESET). RESET is asserted when the voltage at provide a single low-battery output, LBO. LBO asserts VCC falls below the reset threshold level. Reset remains when LTHIN drops below VLTH and remains asserted asserted for the reset timeout period after VCC exceeds for at least 150ms after HTHIN rises above VHTH (see the threshold. If VCC goes below the reset threshold Figure 2). The MAX6848/MAX6849 dual-output voltage before the reset timeout period is completed, the inter- monitors provide two low-battery outputs: LBOH and nal timer restarts (see Figure 4). The MAX6846/ LBOL. LBOH asserts when HTHIN drops below VHTH- MAX6848 have open-drain reset outputs, while the and remains asserted for at least 150ms after HTHIN MAX6847/MAX6849 have push-pull reset outputs. _______________________________________________________________________________________7
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