IRFD110 www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + Circuit layout considerations D.U.T. • Low stray inductance • Ground plane • Low leakage inductance current transformer - + - + - Rg • dV/dt controlled by R + g • Driver same type as D.U.T. V - DD • ISD controlled by duty factor “D” • D.U.T. - device under test Driver gate drive Period P.W. D = P.W. Period V = 10 Va GS D.U.T. l waveform SD Reverse recovery Body diode forward current current dI/dt D.U.T. V waveform DS Diode recovery dV/dt VDD Re-applied voltage Body diode forward drop Inductor current Ripple ≤ 5 % ISD Note a. V = 5 V for logic level devices GS Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91127. S21-0885-Rev. D, 30-Aug-2021 7 Document Number: 91127 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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