Datasheet AS6C6264 (Alliance Memory) - 6

AS6C6264 February 2007 ® Updated July 2017 8K X 8 BIT LOW POWER CMOS SRAM TIMING WAVEFORMS READ CYCLE 1
(Address Controlled) (1,2) tRC Address tAA tOH Dout Previous Data Valid Data Valid
READ CYCLE 2
(CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 OE# tOE tOH tOLZ tOHZ tCLZ tCHZ Dout High-Z Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Page 5 of 12 July 2017, v2.0 Alliance Memory Inc