Datasheet AS6C6264 (Alliance Memory) - 7

February 2007 AS6C6264 ® Updated July 2017 8K X 8 BIT LOW POWER CMOS SRAM WRITE CYCLE 1
(WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tAS tWP tWR WE# tWHZ TOW High-Z Dout (4) (4) tDW tDH Din Data Valid
WRITE CYCLE 2
(CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW CE2 tWP WE# tWHZ High-Z Dout (4) tDW tDH Din Data Valid Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
July 2017, v2.0 Alliance Memory Inc Page 6 of 12