Datasheet AS6C6264 (Alliance Memory) - 8

February 2007 AS6C6264 ® Updated July 2017 8K X 8 BIT LOW POWER CMOS SRAM DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
V CE# ≧ V CC for Data Retention V CC - 0.2V DR or CE2 ≦ 0.2V 1.5 - 5.5 V VCC = 1.5V Data Retention Current IDR CE# ≧ VCC - 0.2V - 0.5 10 µA or CE2 ≦ 0.2V Chip Disable to Data See Data Retention Retention Time tCDR Waveforms (below) 0 - - ns Recovery Time tR tRC* - - ns tRC* = Read Cycle Time
DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1)
(CE# control ed) VDR ≧ 1.5V Vcc(min.) Vcc(min.) Vcc tCDR tR VIH CE# ≧ Vcc-0.2V V CE# IH
Low Vcc Data Retention Waveform (2)
(CE2 control ed) VDR ≧ 1.5V Vcc(min.) Vcc(min.) Vcc tCDR tR CE2 ≦ 0.2V CE2 VIL VIL
July 2017, v2.0 Alliance Memory Inc Page 7 of 12