Datasheet PEMD12, PUMD12 (Nexperia) - 3

link to page 3
NXP Semiconductors PEMD12; PUMD12 NPN/PNP resistor-equipped transistors; R1 = 47 k , R2 = 47 k 2. Pinning information Table 3. Pinning Pin Description Simplified outline Graphic symbol
1 GND (emitter) TR1 6 5 4 6 5 4 2 input (base) TR1 3 output (collector) TR2 4 GND (emitter) TR2 R1 R2 5 input (base) TR2 TR2 1 2 3 TR1 6 output (collector) TR1 001aab555 R2 R1 1 2 3 006aaa143
3. Ordering information Table 4. Ordering information Type number Package Name Description Version
PEMD12 - plastic surface-mounted package; 6 leads SOT666 PUMD12 SC-88 plastic surface-mounted package; 6 leads SOT363
4. Marking Table 5. Marking codes Type number Marking code[1]
PEMD12 D2 PUMD12 D*1 [1] * = placeholder for manufacturing site code PEMD12_PUMD12 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 21 November 2011 2 of 16
Document Outline 1. Product profile 1.1 General description 1.2 Features and benefits 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Marking 5. Limiting values 6. Thermal characteristics 7. Characteristics 8. Test information 8.1 Quality information 9. Package outline 10. Packing information 11. Soldering 12. Revision history 13. Legal information 13.1 Data sheet status 13.2 Definitions 13.3 Disclaimers 13.4 Trademarks 14. Contact information 15. Contents