Datasheet IRFP9140 (Vishay) - 7

IRFP9140
www.vishay.com Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit D.U.T.
+ Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer - + - - + Rg • dV/dt controlled by R + g • I V SD controlled by duty factor “D” - DD • D.U.T. - device under test
Note
• Compliment N-Channel of D.U.T. for driver Driver gate drive Period P.W. D = P.W. Period V = - 10 Va GS D.U.T. l waveform SD Reverse recovery Body diode forward current current dI/dt D.U.T. V waveform DS Diode recovery dV/dt VDD Re-applied voltage Body diode forward drop Inductor current I Ripple ≤ 5 % SD
Note
a. V = - 5 V for logic level and - 3 V drive devices GS
Fig. 18 - For P-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91238. S22-0058-Rev. C, 31-Jan-2022
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Document Number: 91238 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000