Datasheet TSB711, TSB711A TSB712, TSB712A (STMicroelectronics) - 5

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TSB711, TSB711A, TSB712, TSB712A Electrical characteristics Symbol Parameter Conditions Min. Typ. Max. Unit
Power supply rejection ratio 5 V < (VCC+) - (VCC-) < 36 V, VICM = VCC / 2 SVR 100 125 dB 20 log (∆VCC / ∆VIO) -40 °C < T < 125 °C No load, -40 °C < T < 125 °C 120 High level output voltage VOH I (drop voltage from V SOURCE = 2 mA, -40 °C < T < 125 °C 200 CC+) ISOURCE = 15 mA, -40 °C < T < 125 °C 1000 mV No load , -40 °C < T < 125 °C 120 VOL Low level output voltage ISINK = 2 mA, -40 °C < T < 125 °C 200 ISINK = 15 mA , -40 °C < T < 125 °C 1000 VOUT = VCC, T = 25 °C 25 50 ISINK VOUT = VCC, -40 °C < T < 125 °C 20 IOUT mA VOUT = 0 V, T = 25 °C 25 50 ISOURCE VOUT = 0 V, -40 °C < T < 125 °C 20 No load, T = 25 °C 1.8 ICC Supply current by op-amp mA No load, -40 °C < T < 125 °C 3
AC performance
GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 4.5 6 MHz 9 V step, RL = 10 kΩ, CL = 100 pF, AV = 1 V/V, SR Slew rate 2.2 3 V / µs 10% to 90% VIN = 1 Vrms , RL = 10 kΩ, AV = +1, f = 1 kHz, 0.0003 Total harmonic distorsion + BW = 22 kHz THD+N % noise VIN = 1 Vrms , RL = 1 kΩ, AV = +1, f = 1 kHz, 0.00034 BW = 22 kHz VOUT = 5 Vpp, f = 1 kHz, AV = +11, RL = 10 kΩ 125 CR Crosstalk dB VOUT = 5Vpp, f = 10 kHz, AV = +11, RL = 10 kΩ 100 Φm Phase margin At unity gain, 25 °C, 10 kΩ, 100 pF 45 ᵒ CLOAD Capacitive load drive 100 (5) pF f = 10 Hz 20 en Input voltage noise density f = 100 Hz 13 nV/√Hz f = 10 kHz 12 en p-p Input noise voltage 0.1 Hz ≤ f ≤ 10 Hz 0.5 µVPP in Input current noise density f = 1 kHz 0.15 pA/√Hz 1. See Section 5.4 Input offset voltage drift over the temperature in application information. 2. Typical value is based on the VIO drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. See Section 5.5 Long term input offset voltage drift. 3. Current is positive when it is sinked into the op-amp. 4. Iio is defined as |Iibp – Iibn| 5. For higher capacitive values see Figure 25. Phase margin vs. output current at VCC = 36 V, Figure 26. Phase margin vs. capacitive load and Figure 27. Overshoot vs. capacitive load at VCC = 36 V 6. Theoretical value of the input current noise density based on the measurement of the input transistor base current: i n = 2. q.ib
DS12487
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Rev 7 page 5/32
Document Outline TSB711, TSB711A, TSB712, TSB712A 1 Pin description 2 Absolute maximum ratings and operating conditions 3 Electrical characteristics 4 Typical performance characteristics 5 Application information 5.1 Operating voltages 5.2 Input pin voltage range 5.3 Rail-to-rail input stage 5.4 Input offset voltage drift over the temperature 5.5 Long term input offset voltage drift 5.6 EMI rejection 5.7 Maximum power dissipation 5.8 Capacitive load and stability 5.9 PCB layout recommendations 5.10 Decoupling capacitor 6 Typical applications 6.1 Low-side current sensing 7 Package information 7.1 SOT23-5 package information 7.2 MiniSO8 package information 7.3 SO8 package information 8 Ordering information Revision history