Datasheet REF20-Q1 (Texas Instruments) - 4

REF20-Q1
SBOSA80 – DECEMBER 2021
www.ti.com 6 Pin Configuration and Functions
V 1 5 V BIAS REF GND 2 EN 3 4 VIN
Figure 6-1. DDC Package SOT23-5 (Top View) Table 6-1. Pin Functions PIN I/O DESCRIPTION NO. NAME
1 VBIAS Output Bias voltage output (VREF / 2) 2 GND — Ground 3 EN Input Enable (EN ≥ VIN – 0.7 V, device enabled) 4 VIN Input Input supply voltage 5 VREF Output Reference voltage output (VREF) 4 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: REF20-Q1 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Device Comparison Table 6 Pin Configuration and Functions 7 Specifications 7.1 Absolute Maximum Ratings 7.2 ESD Ratings 7.3 Recommended Operating Conditions 7.4 Thermal Information 7.5 Electrical Characteristics 7.6 Typical Characteristics 8 Parameter Measurement Information 8.1 Solder Heat Shift 8.2 Long-Term Stability 8.3 Thermal Hysteresis 8.4 Noise Performance 9 Detailed Description 9.1 Overview 9.2 Functional Block Diagram 9.3 Feature Description 9.3.1 VREF and VBIAS Tracking 9.3.2 Low Temperature Drift 9.3.3 Load Current 9.4 Device Functional Modes 10 Applications and Implementation 10.1 Application Information 10.2 Typical Application 10.2.1 Low-Side, Current-Sensing Application 10.2.1.1 Design Requirements 10.2.1.2 Detailed Design Procedure 10.2.1.2.1 Shunt Resistor 10.2.1.2.2 Differential Amplifier 10.2.1.2.3 Voltage Reference 10.2.1.2.4 Error Calculations 10.2.1.2.5 Application Curves 11 Power-Supply Recommendations 12 Layout 12.1 Layout Guidelines 12.2 Layout Example 13 Device and Documentation Support 13.1 Documentation Support 13.1.1 Related Documentation 13.2 Receiving Notification of Documentation Updates 13.3 Support Resources 13.4 Trademarks 13.5 Electrostatic Discharge Caution 13.6 Glossary 14 Mechanical, Packaging, and Orderable Information