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Datasheet HEF4013B (Nexperia)

ПроизводительNexperia
ОписаниеDual D-Type Flip-Flop
Страниц / Страница14 / 1 — HEF4013B. Dual D-type flip-flop. Rev. 12 — 24 July 2024. Product data …
Формат / Размер файлаPDF / 253 Кб
Язык документаанглийский

HEF4013B. Dual D-type flip-flop. Rev. 12 — 24 July 2024. Product data sheet. 1. General description. 2. Features and benefits

Datasheet HEF4013B Nexperia

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HEF4013B Dual D-type flip-flop Rev. 12 — 24 July 2024 Product data sheet 1. General description
The HEF4013B is a dual D-type flip-flop with set and reset; positive-edge trigger. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. Schmitt-trigger action on the clock input makes the circuit highly tolerant of slower clock rise and fall times.
2. Features and benefits
• Wide supply voltage range from 3.0 V to 15.0 V • CMOS low power dissipation • High noise immunity • Tolerant of slow clock rise and fal times • Fully static operation • 5 V, 10 V, and 15 V parametric ratings • Standardized symmetrical output characteristics • Specified from -40 °C to +125 °C • Complies with JEDEC standard JESD 13-B • ESD protection: • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
3. Applications
• Counters and dividers • Registers • Toggle flip-flops
4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version
HEF4013BT -40 °C to +125 °C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm HEF4013BTT -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; SOT402-1 14 leads; body width 4.4 mm Document Outline 1. General description 2. Features and benefits 3. Applications 4. Ordering information 5. Functional diagram 6. Pinning information 6.1. Pinning 6.2. Pin description 7. Functional description 8. Limiting values 9. Recommended operating conditions 10. Static characteristics 11. Dynamic characteristics 11.1. Waveforms and test circuit 12. Application information 13. Package outline 14. Abbreviations 15. Revision history 16. Legal information Contents
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