Datasheet OPA206, OPA2206, OPA4206 (Texas Instruments) - 10

OPA206, OP A2206, OP A4206
SBOSA11E – MARCH 2020 – REVISED DECEMBER 2023
www.ti.com 5.8 Electrical Characteristics: VS = ±15 V (continued)
at TA = 25°C, VCM = VOUT = midsupply and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT OPEN-LOOP GAIN
RL = 10 kΩ, (V–) + 200 mV < VO < (V+) – 200 mV, 126 132 TA = –40°C to +125°C AOL Open-loop voltage gain dB RL = 2 kΩ, (V–) + 350 mV < VO < (V+) – 350 mV, 126 130 TA = –40°C to +125°C
FREQUENCY RESPONSE
GBW Gain-bandwidth product CL = 30 pF 3.6 MHz SR Slew rate 10-V step, gain = –1 4 V/μs Phase margin RL = 10 kΩ, CL = 25 pF 67 degrees To 0.024% (12-bit), Falling 2.8 tS Settling time 10-V step, gain = 1, μs C Rising 4.5 L = 30 pF Overload recovery time Gain = –10 0.2 μs Total harmonic distortion + THD+N V noise O = 5 VPP, gain = +1, f = 1 kHz, RL = 2 kΩ 0.0004 %
OUTPUT
RL = 10 kΩ (V–) + 0.2 (V+) + 0.2 Voltage output swing from AOL > 126 dB RL = 2 kΩ (V–) + 0.35 (V+) + 0.35 V rail TA = –40°C to +125°C, RL = 10 kΩ (V–) + 0.2 (V+) + 0.2 ISC Short-circuit current ±25 mA CLOAD Capacitive load drive See Typical Characteristics Open-loop output RO See Typical Characteristics impedance
POWER SUPPLY
Quiescent current per 220 240 IQ I μA amplifier O = 0 mA TA = –40°C to +125°C 310 10 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: OPA206 OPA2206 OPA4206 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Pin Configuration and Functions 5 Specifications 5.1 Absolute Maximum Ratings 5.2 ESD Ratings 5.3 Recommended Operating Conditions 5.4 Thermal Information: OPA206 5.5 Thermal Information: OPA2206 5.6 Thermal Information: OPA4206 5.7 Electrical Characteristics: VS = ±5 V 5.8 Electrical Characteristics: VS = ±15 V 5.9 Typical Characteristics 6 Parameter Measurement Information 6.1 Typical Specifications and Distributions 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Input Overvoltage Protection 7.3.2 Input Offset Trimming 7.3.3 Lower Input Bias With Super-Beta Inputs 7.3.4 Overload Power Limiter 7.3.5 EMI Rejection 7.4 Device Functional Modes 8 Application and Implementation 8.1 Application Information 8.2 Typical Applications 8.2.1 Voltage Attenuator 8.2.1.1 Design Requirements 8.2.1.2 Detailed Design Procedure 8.2.1.3 Application Curves 8.2.2 Discrete, Two-Op-Amp Instrumentation Amplifier 8.2.3 Input Buffer and Protection for ADC Driver 8.3 Power Supply Recommendations 8.4 Layout 8.4.1 Layout Guidelines 8.4.2 Layout Example 9 Device and Documentation Support 9.1 Device Support 9.1.1 Development Support 9.1.1.1 PSpice® for TI 9.2 Documentation Support 9.2.1 Related Documentation 9.3 Receiving Notification of Documentation Updates 9.4 Support Resources 9.5 Trademarks 9.6 Electrostatic Discharge Caution 9.7 Glossary 10 Revision History 11 Mechanical, Packaging, and Orderable Information