Datasheet VEML4031X00 (Vishay) - 6

VEML4031X00
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APPLICATION INFORMATION 1. Application Circuit
1.7 V to 3.6 V R1 R2
VEML4031X00 Host Micro Controller
2.5 V to 3.6 V R4 V (4) DD C1 C2 10R 10 μF 100 nF SDA (2) I2C bus data SDA C1 and R4 GND (1) SCL (3) I2C bus clock SCL are optional for a noisy supply Fig. 10 - Application Circuit (x) = Pin Number
Notes
• The interrupt pin is an open drain output. Proposed values for the pull-up resistors should be > 1 kΩ, e.g. 2.2 kΩ to 4.7 kΩ for the R1 and R2 (at SDA and SCL) and 10 kΩ to 100 kΩ for R3 (at interrupt). Normally just one decoupling capacitor is needed. This should be ≥ 100 nF and placed close to the VDD pin. For detailed description about set-up and use of the interrupt as well as more application related information see AN: “Designing VEML4031X00 into an Application”
2. I2C Interface
The VEML4031X00 has eighteen register addresses responsible for operation control, parameter setup and result buffering. All registers are accessible via I2C communication. Fig. 9 shows the basic I2C communication with VEML4031X00. The built in I2C interface is compatible with I2C modes “standard” and “fast”: 10 kHz to 400 kHz. Please refer to the I2C specification from NXP for details. Send byte Block write byte mode 1 7 1 1 8 1 8 1 8 1 8 1 Command code Data byte Data byte Data byte S Slave address Wr A A A A A (address = M) (address = M) (address = M + 1) (address = M + 2) 8 1 8 1 1 Data byte Data byte A A P (address = M + 3) (address = M + N) Receive byte Block read byte mode 1 7 1 1 8 1 1 7 1 1 8 1 8 1 Command code Slave Data byte Data byte S Slave address Wr A A Sr R A A A (address = M) address (address = M) (address = M + 1) 8 1 8 1 1 Data byte Data byte A N P (address = M + 2) (address = M + N) S = start condition Host action P = stop condition A = acknowledge VEML4031X00 response Sr = reapeated start condition Fig. 11 - Send Byte / Receive Byte Protocol Rev. 1.1, 12-Mar-2025
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