Datasheet MAX5362 (Analog Devices) - 3

Low-Cost, Low-Power 6-Bit DACs with 2-Wire Serial Interface in SOT23 Package MAX5360/MAX5361/MAX5362 ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL =10kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS
MAX5360 2.7 3.6 Supply Voltage VDD MAX5361 4.5 5.5 V MAX5362 2.7 5.5 No load, all digital inputs at 0 or VDD, code = 63 150 230 Supply Current IDD µA Shutdown mode 1
DIGITAL INPUTS
(SCL, SDA) Input Low Voltage VIL 0.3 VDD V Input High Voltage VIH 0.7 VDD V Input Hysteresis Vhys 0.05 VDD V Input Capacitance CIN (Note 7) 10 pF Input Leakage Current Ii ±10 µA Pulse Width of Spike Suppressed tSP 0 50 ns
DIGITAL OUTPUT
(SDA) (open drain) ISINK = 3mA 0 0.4 Output Low Voltage VOL V ISINK = 6mA 0 0.6 VIH min to VIL max, ISINK = 3mA 250 Output Fall Time tof bus capacitance ns 10pF to 400pF ISINK = 6mA 250
TIMING CHARACTERISTICS
(VDD = 2.7V to 3.6V (MAX5360); VDD = 4.5V to 5.5V (MAX5361); VDD = 2.7V to 5.5V (MAX5362); RL =10kΩ, CL = 50pF, TA = TMAX to TMIN, Figure 3, unless otherwise noted. Typical values are TA = +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency fSCL 0 400 kHz Bus-Free Time Between a tBUF 1.3 µs STOP and a START Condition Hold Time (Repeated) tHD, STA 0.6 µs START Condition Low Period of the SCL Clock tLOW 1.3 µs High Period of the SCL Clock tHIGH 0.6 µs
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