Datasheet VIA2000SD (Vishay) - 4

VIA2000SD
www.vishay.com Vishay Semiconductors
ELECTRICAL CHARACTERISTICS: VIA2000SD
(VDD1, VDD2 = 3 V to 5.5 V, VIN = 0.1 V to 2 V, and SHTDN = GND1 = 0 V, Tamb = -40 °C to +125 °C) (VDD1 = 5 V, VDD2 = 3.3 V, Tamb = 25 °C, unless otherwise noted)
PARAMETER TEST CONDITION SYMBOL MIN. TYP. MAX. UNIT POWER SUPPLY
Side 1 supply voltage VDD1 3.0 5.0 5.5 V Side 2 supply voltage VDD2 3.0 3.3 5.5 V SHTDN = low - 11.4 15.1 mA Side 1 supply current IDD1 SHTDN = high - 1 - μA Side 2 supply current IDD2 - 6.3 8.4 mA VDD1 undervoltage detection V threshold voltage DD1 falling VDD1_UV 1.8 2.3 2.7 V
ANALOG INPUT
Input offset voltage VIN = 1 V VOS -1.5 ± 0.4 +1.5 mV Input offset drift TCVOS -5 10 30 μV/°C Input resistance RIN - 1 - GΩ Input capacitance fIN = 275 kHz CIN - 7 - pF Input bias current VIN = GND1 IIB -15 3.5 15 nA Input bias current drift TCIIB - ± 10 - pA/°C
ANALOG OUTPUT
Nominal gain - 1 - V/V Gain error EG -0.3 ± 0.05 +0.3 % Gain error thermal drift TCEG -45 ± 5 +45 ppm/°C Non-linearity -0.04 ± 0.01 +0.04 % Non-linearity drift - ± 1 - ppm/°C Total harmonic distortion VIN = 1.8 V, fIN = 10 kHz, BW = 100 kHz THD -87 - dB Output noise VIN = 1 V, BW = 100 kHz - 210 - μVRMS VIN = 1.8 V, fIN = 1 kHz, BW = 10 kHz 78 82 - dB Signal to noise ratio SNR VIN = 1.8 V, fIN = 10 kHz, BW = 100 kHz - 70 - dB Common-mode output voltage VCMout 1.36 1.4 1.45 V Fail-safe differential output voltage SHTDN active or VDD1 missing VFail-Safe - -2.53 -2.44 V Output bandwidth BW - 400 - kHz PSRR vs. VDD1, at DC PSRRDC - -78 - dB PSRR vs. VDD1, 100 mV and 10 kHz ripple PSRRAC - -75 - dB Power supply rejection ratio (1) PSRR vs. VDD2, at DC PSRRDC - -82 - dB PSRR vs. VDD2, 100 mV and 10 kHz ripple PSRRAC - -74 - dB Output resistance ROUT - < 0.2 - Ω Common-mode transient immunity CMTI 100 150 - kV/μs
DIGITAL INPUT (SHTDN)
Input current GND1 ≤ VSHTDN ≤ VDD1 IIN -70 1 μA Input capacitance CIN - 5 - pF High level input voltage VIH 0.7 x VDD1 - VDD1 + 0.3 ppm/°C Low level input voltage VIL -0.3 - 0.3 x VDD1 %
TIMING
Rising time of OUTP, OUTN tr - 1.3 - μs Falling time of OUTP, OUTN tf - 1.3 - μs INP, INN to OUTP, OUTN signal t delay (50 % to 50 %) PD - 1.6 2.1 μs V Analog setting time DD1 step to 3.0 V with VDD2 ≥ 3.0 V, t to OUT AS - 0.5 - ms P, OUTN valid, 0.1 % settling Device enable time SHTDN high to low tEN - 80 100 μs Shutdown time SHTDN low to high tSHTDN - 1.2 5 μs
Note
(1) Input referred Rev. 1.1, 02-Apr-2025
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