Datasheet LT8337 (Analog Devices) - 9

LT8337/LT8337-1
PIN FUNCTIONS SYNC/MODE (Pin 1):
External Synchronization Input and the IC as possible to achieve lowest EMI. Additional bulk Mode Selection Pin. This pin allows five selectable modes capacitors of 2.2µF or more should be placed close to for optimization of performance: the IC with the positive terminals connected to VOUT, and negative terminals connected to ground plane. See the
SYNC/MODE PIN INPUT CAPABLE MODE(S) OF OPERATION
Applications Information section for a sample layout. (1) GND or <0.1V Burst (2) 50k Resistor to GND Burst/SSFM
SW (Pins 9, 10, 11):
The SW pins are the outputs of (3) Float (Pin Open) Pulse-Skipping the internal power switches. Tie these pins together and (4) INTV connect them to the inductor and one side of the boost CC or > (INTVCC–0.2V) Pulse-Skipping/SSFM (5) External Clock Pulse-Skipping/Sync capacitor CBST.
BST (Pin 12):
Top Switch Gate Driver Supply Pin. Place where the selectable modes of operation are: a 0.1µF capacitor (CBST) between the BST and SW pins Burst = low IQ, (low output ripple operation at light loads) and close to the IC. Pulse-Skipping = skipped pulse(s) at light load (aligned clock)
V
SSFM = spread spectrum frequency modulation for low EMI
IN (Pin 13):
Input Supply Pin. This pin must be con- nected to the input of the power stage (the inductor’s Sync = switching frequency synchronized to external clock. input terminal). The LT8337/LT8337-1 automatically selects pulse-skip-
EN/UVLO (Pin 14):
Enable and Input Undervoltage ping mode with no spread spectrum frequency modu- Lockout Pin. The IC is shut down when this pin is below lation during start-up, and The SYNC/MODE pin input 1V (typical). The IC draws a low V configurations (1) through (4) are ignored. IN current of 0.3μA (typical) when this pin is below 0.15V. The IC is enabled The LT8337/LT8337-1 automatically select low IQ opera- when this pin is above 1.0V (typical). A resistor divider tion in the PassThru mode operation, and all the SYNC/ from VIN to GND can be used to program a VIN threshold MODE pin input configurations are ignored. below which the IC is shut down. See the Applications
RT (Pin 2):
Switching Frequency Adjustment Pin. The Information section for further details. Tie EN/UVLO to LT8337/LT8337-1 switching frequency is programmed VIN if the shutdown feature is not used. by connecting a resistor of the appropriate value from the
INTVCC (Pin 15):
Internal 3.5V Regulator Bypass Pin. RT pin to GND at Pin 3. See the Applications Information This pin provides supply for internal drivers and control section for more detail. Do not leave the RT pin open. circuits. The bypass capacitor for INTVCC should be con-
GND (Pins 3, 5, 8, Exposed Pad Pin 17):
Ground. The nected to the ground plane. Do not load the INTVCC pin exposed pad should be soldered to the PCB ground plane with external circuitry. This pin must be bypassed with a for good thermal and electrical performance. See the 1µF or larger low ESR ceramic capacitor placed close to Applications Information section for sample layout. the pin.
FB (Pin 4):
Feedback Input Pin. This pin receives the feed-
PG (Pin 16, LT8337 Only):
Power Good Indicator. Open- back voltage from the external resistor divider between drain logic output that is pulled to ground when the output V voltage is greater than ±8% outside the regulated volt- OUT and Pin 3 GND. FB pin is one input to the error amplifier of the output voltage control loop. See the age. PG is also pulled to ground when EN/UVLO is below Applications Information section for sample layout. 1V, INTVCC has fallen too low, or the IC enters thermal shutdown.
VOUT (Pins 6, 7):
Output Pins. Connect one 1µF capaci- tor between V
VC (Pin 16, LT8337-1 Only):
Error Amplifier Output and OUT at Pin 6 and GND at Pin 5 only, and a matching 1µF capacitor between V Switch Regulator Compensation Pin. Connect this pin to OUT at Pin 7 and GND at Pin 8 only. These two capacitors complete the Silent appropriate external RC network to compensate the regu- Switcher configuration and must be placed as close to lator loop frequency response. Rev. A For more information www.analog.com 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts