Datasheet BD14230FVJ-C (Rohm) - 8

BD1423x-C Series Timing Chart
1. Control Sequence 1.1 Power supply start-up sequence VDD VDD (Min) tOEN OUT Unstable Normal Operation Figure 7. Timing Chart at Power ON Stable time of OUT (tOEN) should be 1 ms or more. 1.2 Power supply off sequence tPSL VDD (Min) VDD t 0.4 V OEN OUT Normal Operation Unstable Normal Operation Figure 8. Timing Chart at Power OFF Power off time (tPSL) should be 1 ms or more. If VDD is under the recommended operating condition, LSI is unstable state. In that case, set Power OFF and ON again. When the power is ON again, the period of VDD < 0.4 V should be tPSL or more. www.rohm.com
TSZ02201-0M2M0FC23020-1-2
© 2022 ROHM Co., Ltd. All rights reserved. 8/17 TSZ22111 • 15 • 001
03.Apr.2025 Rev.002
Document Outline General Description Features Applications Key Specifications Package Typical Application Circuit Pin Configuration Pin Descriptions Absolute Maximum Ratings Thermal Resistance Recommended Operating Conditions Electrical Characteristics Typical Performance Curves Timing Chart Application Examples I/O Equivalence Circuits Operational Notes Ordering Information Marking Diagram Physical Dimension and Packing Information Revision History