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Datasheet PSMN9R0-30YL (Nexperia) - 5

ПроизводительNexperia
ОписаниеN-channel 30 V 8 mΩ logic level MOSFET in LFPAK
Страниц / Страница14 / 5 — NXP Semiconductors. PSMN9R0-30YL. N-channel 30 V 8 mΩ logic level MOSFET …
Версия10201103
Формат / Размер файлаPDF / 394 Кб
Язык документаанглийский

NXP Semiconductors. PSMN9R0-30YL. N-channel 30 V 8 mΩ logic level MOSFET in LFPAK. Characteristics. Table 6. Symbol. Parameter

NXP Semiconductors PSMN9R0-30YL N-channel 30 V 8 mΩ logic level MOSFET in LFPAK Characteristics Table 6 Symbol Parameter

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Труба MOS, Trans MOSFET N-CH 30V 61A 5Pin(4+Tab) LFPAK T/R
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PSMN9R0-30YL,115
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PSMN9R0-30YL
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NXP Semiconductors PSMN9R0-30YL N-channel 30 V 8 mΩ logic level MOSFET in LFPAK 6. Characteristics Table 6. Characteristics
Tested to JEDEC standards where applicable.
Symbol Parameter Conditions Min Typ Max Unit Static characteristics
V(BR)DSS drain-source ID = 250 µA; VGS = 0 V; Tj = 25 °C 30 - - V breakdown voltage ID = 250 µA; VGS = 0 V; Tj = -55 °C 27 - - V VGS(th) gate-source threshold ID = 1 mA; VDS = VGS; Tj = 25 °C; 1.3 1.7 2.15 V voltage see Figure 11; see Figure 12 ID = 1 mA; VDS = VGS; Tj = 150 °C; 0.65 - - V see Figure 12 ID = 1 mA; VDS = VGS; Tj = -55 °C; - - 2.45 V see Figure 12 IDSS drain leakage current VDS = 30 V; VGS = 0 V; Tj = 25 °C - - 1 µA VDS = 30 V; VGS = 0 V; Tj = 150 °C - - 100 µA IGSS gate leakage current VGS = 16 V; VDS = 0 V; Tj = 25 °C - - 100 nA VGS = -16 V; VDS = 0 V; Tj = 25 °C - - 100 nA RDSon drain-source on-state VGS = 4.5 V; ID = 15 A; Tj = 25 °C - 8.77 11.03 mΩ resistance VGS = 10 V; ID = 15 A; Tj = 150 °C; - - 15 mΩ see Figure 13 VGS = 10 V; ID = 15 A; Tj = 25 °C - 6.16 8 mΩ RG gate resistance f = 1 MHz - 0.6 1.5 Ω
Dynamic characteristics
QG(tot) total gate charge ID = 10 A; VDS = 12 V; VGS = 10 V; - 17.8 - nC see Figure 14; see Figure 15 ID = 0 A; VDS = 0 V; VGS = 4.5 V - 7 - nC ID = 10 A; VDS = 12 V; VGS = 4.5 V; - 8.7 - nC see Figure 14 QGS gate-source charge ID = 10 A; VDS = 12 V; VGS = 4.5 V; - 3 - nC see Figure 14; see Figure 15 QGS(th) pre-threshold - 1.7 - nC gate-source charge QGS(th-pl) post-threshold - 1.3 - nC gate-source charge QGD gate-drain charge - 2.4 - nC VGS(pl) gate-source plateau VDS = 12 V; see Figure 14; - 2.7 - V voltage see Figure 15 Ciss input capacitance VDS = 12 V; VGS = 0 V; f = 1 MHz; - 1006 - pF Tj = 25 °C; see Figure 16 Coss output capacitance - 227 - pF Crss reverse transfer - 119 - pF capacitance td(on) turn-on delay time VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V; - 13 - ns RG(ext) = 4.7 Ω tr rise time - 28 - ns td(off) turn-off delay time - 19 - ns tf fall time - 9 - ns PSMN9R0-30YL All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 04 — 9 March 2011 5 of 14
Document Outline 1. Product profile 1.1 General description 1.2 Features and benefits 1.3 Applications 1.4 Quick reference data 2. Pinning information 3. Ordering information 4. Limiting values 5. Thermal characteristics 6. Characteristics 7. Package outline 8. Revision history 9. Legal information 9.1 Data sheet status 9.2 Definitions 9.3 Disclaimers 9.4 Trademarks 10. Contact information 11. Contents
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