DATA SHEETSKY53510/SKY53580/SKY53540 Low-Power DC to 3.1 GHz Ultra-Low Additive Jitter Differential Clock Buffers The SKY53510/80/40 family of fanout buffers is ideal • Two banks of differential output clocks for high-frequency, low-jitter clock distribution. - 10/8/4 output ordering options These devices feature universal level format - Pin-selectable output formats (per bank): translation and ultra-low additive RMS phase jitter LVPECL, LVDS, HCSL over a wide range of conditions, including frequency • Frequency range: and input clock slew rate. - LVPECL: dc to 3.1 GHz Separate core and output voltages are included, - LVDS : d c to 3 GHz supporting down to 1.8 V to enable additional power - HCSL: dc to 800 MHz savings. • PCIe Gen1/2/3/4/5/6/7 compliant • Low-power operation (VDD/VDDO) Built-in LDOs deliver high PSRR performance and - 1.8 V/2.5 V/3.3 V reduce the need for external components, simplifying • LVCMOS output with synchronous enable/disable low-jitter clock distribution in noisy environments. • Temperature range: The SKY53510/80/40 features a selectable input clock - –40 to +95 °C ambient temperature using a 3:1 input mux, one single-ended output, and - 105 °C max board temperature either 10, 8, or 4 differential outputs in two banks, • Packages: each of which is selectable as LVPECL, LVDS, HCSL, or - SKY53510: 48-pin, 7 x 7 mm QFN tristate and whose voltage supply is independently - SKY53580: 40-pin, 6 x 6 mm QFN sourced with either 1.8 V, 2.5 V, or 3.3 V. - SKY53540: 32-pin, 5 x 5 mm QFN Each output bank has its own dedicated 1.8 V, 2.5 V, or • For RoHS and other product compliance 3.3 V output voltage supply. This buffer family can be information, see the Skyworks Certificate of paired with the Skyworks NetSync™ family of network Conformance. synchronizer clocks, jitter attenuators, and clock generators and oscillators to deliver ultra-low-jitter clock tree solutions. Key Features • Ultra-low additive jitter (156.25 MHz LVPECL, 12 kHz to 20 MHz): - 35 fs RMS typical - 47 fs RMS max • 3:1 Input multiplexer - Two any-format universal inputs supporting LVPECL, LVDS, S-LVDS, HCSL, CML, SSTL, and HSTL - One crystal input (also accepts a single-ended clock) Skyworks Solutions, Inc. • Phone [949] 231-3000 • sales@skyworksinc.com • www.skyworksinc.com 207106A • Skyworks Proprietary Information • Products and Product Information are Subject to Change without Notice 1 August 1, 2025 Document Outline Key Features 1. Pin Descriptions 1.1. SKY53510 7x7 mm 48-QFN Pin Descriptions 1.2. SKY53580 6x6 mm 40-QFN Pin Descriptions 1.3. SKY53540 5x5 mm 32-QFN Pin Descriptions 2. Detailed Description 2.1. Overview 2.2. Block Diagrams 2.3. Modes of Operation 2.3.1. Input Clock Stage 2.3.2. Clock Outputs 3. Applications Information 3.1. Driving Clock Inputs (CLK0/CLK1) 3.2. Crystal Interface (XA/XB) 3.3. Clock Output Termination 3.3.1. DC-Coupled Differential Output Driver Terminations 3.3.2. AC-Coupled Differential Output Driver Terminations 4. Power Supply (VDD and VDDOx) 4.1. Power Supply Sequencing 5. Electrical Specifications 6. Typical Performance Characteristics 7. Package and Handling Information 7.1. 48-QFN Package Diagram 7.2. 40-QFN Package Diagram 7.3. 32-QFN Package Diagram 8. Land Patterns 8.1. 48-QFN Land Pattern 8.2. 40-QFN Land Pattern 8.3. 32-QFN Land Pattern 9. Top Markings 9.1. SKY53510/80/40 Top Markings 10. Ordering Guide 11. Revision History
