BA76220PIR ControllerPin DescriptionPin No.Pin NameTypeInternalConnectionDescription 1 OP1P AI PMOS OP1 non-inverting input 2 OP1NC AI PMOS Capacitor connected to OP1 inverting input 3 OP1N AI PMOS OP1 inverting input 4 OP1O AO CMOS OP1 output 5 OP2NC AI PMOS Capacitor connected to OP2 inverting input 6 OP2N AI PMOS OP2 inverting input 7 OP2O AO CMOS OP2 output 8 VREG AO NMOS Regulator voltage 9 VSS PWR — Negative power supply, ground 10 VDD PWR — Positive power supply OUTPUT and VPP share the same pin 11 OUTPUT/VPP DO/PWR CMOS ● Output to drive, active high ● Programming ROM power supply 12 DT AI PMOS Delay time oscillator input. Connected to an external RC to adjust output duration TEST and SC share the same pin 13 TEST/SC DO CMOS ● TEST is used to test the 32kHz system frequency ● SC is used to detect LVD and CDS CDS and RX/TX share the same pin ● CDS is connected to a CDS voltage divider for daytime/night 14 CDS/RX/TX AI/DI/DO CMOS auto-detection. A low input to this pin can disable the PIR input ● Write data & read data 15 NC — — Not connected ● Operating mode selection input VDD: Output is always ON 16 MODE AI CMOS VSS: Output is always OFF OPEN: Auto detection ● Input for Test mode Legend: DI: Digital Input; DO: Digital Output; AI: Analog Input; AO: Analog Output; PWR: Power Absolute Maximum Ratings Supply Voltage ...VSS-0.3V to 6.0V Input Voltage ...VSS-0.3V to VDD+0.3V Storage Temperature ... -60°C to 150°C Operating Temperature ... -40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of the device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 5 September 08, 2025 Document Outline Features Applications General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings Electrical Characteristics Functional Description TEST SC DT MODE CDS OUTPUT LVD Trigger Timing Retrigger LVD & CDS Detect Circuit The Criterion of LVD and CDS The Criterion of MODE Conditions for Disabling the PIR Amplifier Circuit Selection of OSC or DT Write ROM & Data Updated Communication Write/Read Value Protocol Registers PIR Amplifier Power-on Flow Application Circuits OTP-based Application Circuit RC-based Application Circuit Package Information 16-pin NSOP (150mil) Outline Dimensions
