BA76220PIR ControllerLVD The LVD is a low voltage detector. When the detected voltage is less than VL, the OUTPUT will be toggled. As shown below, assume RX, RLVD can be adjusted to obtain the desired voltage detection level. Users can select VL by the LVD register. VDD RX (1/3)VDD + Comparator VL - RLVD TEST/SC LVD Application ExampleTrigger Timing The effective input trigger signal width should be ≥ 24ms. The output is valid either with (1) trigger signal width ≥ 0.5 seconds or (2) more than 2 effective trigger inputs within 2 seconds (separation of 2 triggers ≥ 0.5s). And the separation time between two OUTPUT pin turn-on time must be more than 1 sec. The trigger timing is shown below. <2s <24ms >24ms >0.5s >0.5s Trigger Input >24ms DT Delay Time OUTPUT ON ON >1sec OSC Trigger Timing Rev. 1.00 9 September 08, 2025 Document Outline Features Applications General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings Electrical Characteristics Functional Description TEST SC DT MODE CDS OUTPUT LVD Trigger Timing Retrigger LVD & CDS Detect Circuit The Criterion of LVD and CDS The Criterion of MODE Conditions for Disabling the PIR Amplifier Circuit Selection of OSC or DT Write ROM & Data Updated Communication Write/Read Value Protocol Registers PIR Amplifier Power-on Flow Application Circuits OTP-based Application Circuit RC-based Application Circuit Package Information 16-pin NSOP (150mil) Outline Dimensions
