BA76220PIR ControllerRetrigger When the output of the comparator is a valid signal, the OUTPUT pin will be activated and the active duration is controlled by the DT oscillating period. If the previous “Delay Time tD” has not been over yet and the next valid signal occurs again, the active duration of the OUTPUT pin will be restarted to count. The timing is shown below. + Trigger Level Comparator Input Comparator >24ms >24ms - Trigger Level Output <2s <2s <2s tD DT tD tD OUTPUT ON ON RetriggerLVD & CDS Detect Circuit The external and internal detecting circuits for LVD and CDS are shown below respectively. When the input voltage VLVD is less than VL, the comparator outputs a low level and it means that the VDD is less than minimum operating voltage (VMIN). When the VCDS is less than VC, the comparator outputs high level and it means that it is daytime, otherwise it is night. Where VLVD = RLVD R VDD LVD + RX VCDS = RCDS R VREG CDS + RY VDD VREG RX RY CDS RLVD RCDS TEST/SC CDS & LVD Application Circuit Rev. 1.00 10 September 08, 2025 Document Outline Features Applications General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings Electrical Characteristics Functional Description TEST SC DT MODE CDS OUTPUT LVD Trigger Timing Retrigger LVD & CDS Detect Circuit The Criterion of LVD and CDS The Criterion of MODE Conditions for Disabling the PIR Amplifier Circuit Selection of OSC or DT Write ROM & Data Updated Communication Write/Read Value Protocol Registers PIR Amplifier Power-on Flow Application Circuits OTP-based Application Circuit RC-based Application Circuit Package Information 16-pin NSOP (150mil) Outline Dimensions
