Datasheet Si5351 (Silicon Labs) - 8

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S i 5 3 5 1 A / B / C - B Table 7. Crystal Requirements1,2 Parameter Symbol Min Typ Max Unit
Crystal Frequency fXTAL 25 — 27 MHz Load Capacitance CL 6 — 12 pF Equivalent Series Resistance rESR — — 150 Crystal Max Drive Level dL 100 — — µW
Notes: 1.
Crystals which require load capacitances of 6, 8, or 10 pF should use the device’s internal load capacitance for optimum performance. See register 183 bits 7:6. A crystal with a 12 pF load capacitance requirement should use a combination of the internal 10 pF load capacitance in addition to external 2 pF load capacitance (e.g., by using 4 pF capacitors on XA and XB).
2.
Refer to “AN551: Crystal Selection Guide” for more details.
Table 8. I2C Specifications (SCL,SDA)1 Parameter Symbol Test Condition Standard Mode Fast Mode Unit 100 kbps 400 kbps Min Max Min Max
LOW Level 0.3 x V V DDI2 –0.5 0.3 x V 2 V Input Voltage ILI2C –0.5 DDI2C C HIGH Level 0.7 x V V DDI2 3.6 0.7 x V 2 3.6 V Input Voltage IHI2C DDI2C C Hysteresis of Schmitt Trigger VHYS — — 0.1 — V Inputs LOW Level Output Voltage (open drain or V 2 V 2 = 2.5/3.3 V 0 0.4 0 0.4 V open collector) OLI2C DDI2C at 3 mA Sink Current Input Current III2C –10 10 –10 10 µA Capacitance for C Each I/O Pin II2C VIN = –0.1 to VDDI2C — 4 — 4 pF I2C Bus T Timeout TO Timeout Enabled 25 35 25 35 ms
Notes: 1.
Refer to NXP’s UM10204 I2C-bus specification and user manual, revision 03, for further details, go to: www.nxp.com/acrobat_download/usermanuals/UM10204_3.pdf.
2.
Only I2C pullup voltages (VDDI2C) of 2.25 to 3.63 V are supported.
8 Rev. 1.0
Document Outline 1. Electrical Specifications 2. Detailed Block Diagrams 3. Functional Description 3.1. Input Stage 3.1.1. Crystal Inputs (XA, XB) 3.1.2. External Clock Input (CLKIN) 3.1.3. Voltage Control Input (VC) 3.2. Synthesis Stages 3.3. Output Stage 3.4. Spread Spectrum 3.5. Control Pins (OEB, SSEN) 3.5.1. Output Enable (OEB) 3.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B only 4. I2C Interface 5. Configuring the Si5351 5.1. Writing a Custom Configuration to RAM 5.2. Si5351 Application Examples 5.3. Replacing Crystals and Crystal Oscillators 5.4. Replacing Crystals, Crystal Oscillators, and VCXOs 5.5. Replacing Crystals, Crystal Oscillators, and PLLs 5.6. Applying a Reference Clock at XTAL Input 5.7. HCSL Compatible Outputs 6. Design Considerations 6.1. Power Supply Decoupling/Filtering 6.2. Power Supply Sequencing 6.3. External Crystal 6.4. External Crystal Load Capacitors 6.5. Unused Pins 6.6. Trace Characteristics 7. Register Map Summary 8. Register Descriptions 9. Si5351 Pin Descriptions 9.1. Si5351A 20-pin QFN 9.2. Si5351B 20-Pin QFN 9.3. Si5351C 20-Pin QFN 9.4. Si5351A 10-Pin MSOP 10. Ordering Information 11. Package Outlines 11.1. 20-pin QFN 12. Land Pattern: 20-Pin QFN 12.1. 10-Pin MSOP Package Outline 13. Land Pattern: 10-Pin MSOP 14. Top Marking 14.1. 20-Pin QFN Top Marking 14.2. Top Marking Explanation 14.3. 10-Pin MSOP Top Marking 14.4. Top Marking Explanation Document Change List