Datasheet Si5351 (Skyworks) - 8

Si5351A/B/C-B 3. Electrical Specifications Table 3. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit
Ambient Temperature TA –40 25 85 °C 3.0 3.3 3.60 V Core Supply Voltage VDD 2.25 2.5 2.75 V 1.71 1.8 1.89 V Output Buffer Voltage VDDOx 2.25 2.5 2.75 V 3.0 3.3 3.60 V
Notes:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted. VDD and VDDOx can be operated at independent voltages. Power supply sequencing for VDD and VDDOx requires that all VDDOx be powered up either before or at the same time as VDD.
Table 4. DC Characteristics
(VDD = 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Enabled 3 outputs — 22 35 mA Core Supply Current IDD Enabled 4 outputs — 24 38 mA Enabled 8 outputs — 27 45 mA Output Buffer Supply Current I (Per Output)* DDOx CL = 5 pF — 2.2 5.6 mA CLKIN, SDA, SCL ICLKIN — — 10 µA Input Current Vin < 3.6 V IVC VC — — 30 µA 3.3 V VDDO, default high Output Impedance ZO — 50 — drive
*Note:
Output clocks less than or equal to 100 MHz. 8 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.3 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • August 27, 2021 Document Outline 1. Ordering Guide 2. Technical Support Resources 3. Electrical Specifications 4. Functional Description 4.1. Input Stage 4.1.1. Crystal Inputs (XA, XB) 4.1.2. External Clock Input (CLKIN) 4.1.3. Voltage Control Input (VC) 4.2. Synthesis Stages 4.3. Output Stage 4.4. Spread Spectrum 4.5. Control Pins (OEB, SSEN) 4.5.1. Output Enable (OEB) 4.5.2. Spread Spectrum Enable (SSEN)—Si5351A and Si5351B Only 4.6. Status Pins (INTR) 5. I2C Interface 6. Configuring the Si5351 6.1. Writing a Custom Configuration to RAM 6.2. Si5351 Application Examples 6.3. Replacing Crystals and Crystal Oscillators 6.4. Replacing Crystals, Crystal Oscillators, and VCXOs 6.5. Replacing Crystals, Crystal Oscillators, and PLLs 6.6. Applying a Reference Clock at XTAL Input 6.7. HCSL Compatible Outputs 7. Design Considerations 7.1. Power Supply Decoupling/Filtering 7.2. Power Supply Sequencing 7.3. External Crystal 7.4. External Crystal Load Capacitors 7.5. Unused Pins 7.6. Trace Characteristics 8. Register Map Summary 9. Register Descriptions 10. Si5351 Pin Descriptions 10.1. Si5351A 20-pin QFN 10.2. Si5351B 20-Pin QFN 10.3. Si5351C 20-Pin QFN 10.4. Si5351A 16-Pin QFN 10.5. Si5351B 16-Pin QFN 10.6. Si5351C 16-Pin QFN 10.7. Si5351A 10-Pin MSOP 11. Ordering Information 12. Packaging 12.1. 20-pin QFN Package Outline 12.2. Land Pattern: 20-Pin QFN 12.3. 16-Pin QFN Package Outline 12.4. Land Pattern: 16-Pin QFN 12.5. 10-Pin MSOP Package Outline 12.6. Land Pattern: 10-Pin MSOP 13. Top Marking 13.1. 20-Pin QFN Top Marking 13.2. Top Marking Explanation 13.3. 16-Pin QFN Top Marking 13.4. Top Marking Explanation 13.5. 10-Pin MSOP Top Marking 13.6. Top Marking Explanation Revision History