Datasheet GD32E103xx (GigaDevice) - 9

GD32E103xx Datasheet
2. Device overview 2.1. Device information Table 2-1. GD32E103xx devices features and peripheral list GD32E103xx Part Number T8 TB C8 CB R8 RB V8 VB Flash (KB)
64 128 64 128 64 128 64 128
SRAM (KB)
20 32 20 32 20 32 20 32
General timer(16-
4 4 10 10 10 10 10 10
bit)
(1-4) (1-4) (1-4,8-13) (1-4,8-13) (1-4,8-13) (1-4,8-13) (1-4,8-13) (1-4,8-13)
Advanced
1 1 1 1 2 2 2 2
timer(16-bit)
(0) (0) (0) (0) (0,7) (0,7) (0,7) (0,7)
rs e SysTick
1 1 1 1 1 1 1 1
m Ti
2 2 2 2 2 2 2 2
Basic timer(16-bit)
(5,6) (5,6) (5,6) (5,6) (5,6) (5,6) (5,6) (5,6)
Watchdog
2 2 2 2 2 2 2 2
RTC
1 1 1 1 1 1 1 1 2 2 3 3 3 3 3 3
USART
(0-1) (0-1) (0-2) (0-2) (0-2) (0-2) (0-2) (0-2) 2 2 2 2
UART
0 0 0 0
ity
(3-4) (3-4) (3-4) (3-4)
tiv c e
1 1 2 2 2 2 2 2
I2C
(0) (0) (0-1) (0-1) (0-1) (0-1) (0-1) (0-1)
Conn
1/0 1/0 3/2 3/2 3/2 3/2 3/2 3/2
SPI/I2S
(0/-) (0/-) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2) (0-2)/(1-2)
USBFS
1 1 1 1 1 1 1 1
GPIO
26 26 37 37 51 51 80 80
EXMC
0 0 0 0 0 0 1 1
EXTI
16 16 16 16 16 16 16 16
Units
2 2 2 2 2 2 2 2
ADC Channels
10 10 10 10 16 16 16 16
Units
1 1 1 1 1 1 1 1
DAC Channels
2 2 2 2 2 2 2 2
Package
QFN36 LQFP48 LQFP64 LQFP100 8 Document Outline Table of Contents List of Figures List of Tables 1. General description 2. Device overview 2.1. Device information 2.2. Block diagram 2.3. Pinouts and pin assignment 2.4. Memory map 2.5. Clock tree 2.6. Pin definitions 2.6.1. GD32E103Vx LQFP100 pin definitions 2.6.2. GD32E103Rx LQFP64 pin definitions 2.6.3. GD32E103Cx LQFP48 pin definitions 2.6.4. GD32E103Tx QFN36 pin definitions 3. Functional description 3.1. Arm® Cortex®-M4 core 3.2. On-chip memory 3.3. Clock, reset and supply management 3.4. Boot modes 3.5. Power saving modes 3.6. Analog to digital converter (ADC) 3.7. Digital to analog converter (DAC) 3.8. DMA 3.9. General-purpose inputs/outputs (GPIOs) 3.10. Timers and PWM generation 3.11. Real time clock (RTC) 3.12. Inter-integrated circuit (I2C) 3.13. Serial peripheral interface (SPI) 3.14. Universal synchronous asynchronous receiver transmitter (USART) 3.15. Inter-IC sound (I2S) 3.16. Universal serial bus full-speed interface (USBFS) 3.17. External memory controller (EXMC) 3.18. Debug mode 3.19. Package and operation temperature 4. Electrical characteristics 4.1. Absolute maximum ratings 4.2. Operating conditions characteristics 4.3. Power consumption 4.4. EMC characteristics 4.5. Power supply supervisor characteristics 4.6. Electrical sensitivity 4.7. External clock characteristics 4.8. Internal clock characteristics 4.9. PLL characteristics 4.10. Memory characteristics 4.11. NRST pin characteristics 4.12. GPIO characteristics 4.13. ADC characteristics 4.14. Temperature sensor characteristics 4.15. DAC characteristics 4.16. I2C characteristics 4.17. SPI characteristics 4.18. I2S characteristics 4.19. USART characteristics 4.20. USBFS characteristics 4.21. EXMC characteristics 4.22. TIMER characteristics 4.23. WDGT characteristics 4.24. Parameter conditions 5. Package information 5.1. LQFP100 package outline dimensions 5.2. LQFP64 package outline dimensions 5.3. LQFP48 package outline dimensions 5.4. QFN36 package outline dimensions 5.5. Thermal characteristics 6. Ordering information 7. Revision history