User Manual GD32E103xx (GigaDevice)

GigaDevice Semiconductor Inc. GD32E10x ARM® Cortex®-M4 32-bit MCU For GD32E103xx User Manual
Revision 2.1 ( Feb. 2025 ) Document Outline Table of Contents List of Figures List of Tables 1. System and memory architecture 1.1. ARM Cortex-M4 processor 1.2. System architecture 1.3. Memory map 1.3.1. Bit-banding 1.3.2. On-chip SRAM memory 1.3.3. On-chip flash memory overview 1.4. Boot configuration 1.5. Device electronic signature 1.5.1. Memory density information 1.5.2. Unique device ID (96 bits) 1.6. System configuration registers 2. Flash memory controller (FMC) 2.1. Overview 2.2. Characteristics 2.3. Function overview 2.3.1. Flash memory architecture 2.3.2. Read operations Wait state added: Current buffer: Pre-fetch buffer: IBUS Cache: DBUS Cache: 2.3.3. Unlock the FMC_CTL register 2.3.4. Page erase 2.3.5. Mass erase 2.3.6. Main flash programming 2.3.7. OTP programming 2.3.8. Option bytes Erase 2.3.9. Option bytes modify 2.3.10. Option bytes description 2.3.11. Page erase/program protection 2.3.12. Security protection 2.4. Register definition 2.4.1. Wait state register (FMC_WS) 2.4.2. Unlock key register (FMC_KEY) 2.4.3. Option byte unlock key register (FMC_OBKEY) 2.4.4. Status register (FMC_STAT) 2.4.5. Control register (FMC_CTL) 2.4.6. Address register (FMC_ADDR) 2.4.7. Option byte status register (FMC_OBSTAT) 2.4.8. Erase/Program protection register (FMC_WP) 2.4.9. Product ID register (FMC_PID) 3. Power management unit (PMU) 3.1. Overview 3.2. Characteristics 3.3. Function overview 3.3.1. Backup domain 3.3.2. VDD / VDDA power domain VDD domain VDDA domain 3.3.3. 1.2V power domain 3.3.4. Power saving modes Sleep mode Deep-sleep mode Standby mode 3.4. Register definition 3.4.1. Control register (PMU_CTL) 3.4.2. Control and status register (PMU_CS) 4. Backup unit (BKP) 4.1. Overview 4.2. Characteristics 4.3. Function overview 4.3.1. RTC clock calibration 4.3.2. Tamper detection 4.4. Register definition 4.4.1. Backup data register x (BKP_DATAx) (x= 0..41) 4.4.2. RTC signal output control register (BKP_OCTL) 4.4.3. Tamper pin control register (BKP_TPCTL) 4.4.4. Tamper control and status register (BKP_TPCS) 5. Reset and clock unit (RCU) 5.1. Reset control unit (RCTL) 5.1.1. Overview 5.1.2. Function overview Power reset System reset Backup domain reset 5.2. Clock control unit (CCTL) 5.2.1. Overview 5.2.2. Characteristics 5.2.3. Function overview High speed crystal oscillator (HXTAL) Internal 8M RC oscillators (IRC8M) Internal 48M RC oscillators (IRC48M) Phase locked loop (PLL) Low speed crystal oscillator (LXTAL) Internal 40K RC oscillator (IRC40K) System clock (CK_SYS) selection HXTAL clock monitor (CKM) Clock output capability Voltage control 5.3. Register definition 5.3.1. Control register (RCU_CTL) 5.3.2. Clock configuration register 0 (RCU_CFG0) 5.3.3. Clock interrupt register (RCU_INT) 5.3.4. APB2 reset register (RCU_APB2RST) 5.3.5. APB1 reset register (RCU_APB1RST) 5.3.6. AHB enable register (RCU_AHBEN) 5.3.7. APB2 enable register (RCU_APB2EN) 5.3.8. APB1 enable register (RCU_APB1EN) 5.3.9. Backup domain control register (RCU_BDCTL) 5.3.10. Reset source/clock register (RCU_RSTSCK) 5.3.11. AHB reset register (RCU_AHBRST) 5.3.12. Clock configuration register 1 (RCU_CFG1) 5.3.13. Deep-sleep mode voltage register (RCU_DSV) 5.3.14. Additional clock control register (RCU_ADDCTL) 5.3.15. Additional clock interrupt register (RCU_ADDINT) 5.3.16. APB1 additional reset register (RCU_ADDAPB1RST) 5.3.17. APB1 additional enable register (RCU_ADDAPB1EN) 6. Clock trim controller (CTC) 6.1. Overview 6.2. Characteristics 6.3. Function overview 6.3.1. Reference sync pulse generator 6.3.2. CTC trim counter 6.3.3. Frequency evaluation and automatic trim process 6.3.4. Software program guide 6.4. Register definition 6.4.1. Control register 0 (CTC_CTL0) 6.4.2. Control register 1 (CTC_CTL1) 6.4.3. Status register (CTC_STAT) 6.4.4. Interrupt clear register (CTC_INTC) 7. Interrupt / event controller (EXTI) 7.1. Overview 7.2. Characteristics 7.3. Function overview 7.4. External interrupt and event block diagram 7.5. External interrupt and event function overview 7.6. Register definition 7.6.1. Interrupt enable register (EXTI_INTEN) 7.6.2. Event enable register (EXTI_EVEN) 7.6.3. Rising edge trigger enable register (EXTI_RTEN) 7.6.4. Falling edge trigger enable register (EXTI_FTEN) 7.6.5. Software interrupt event register (EXTI_SWIEV) 7.6.6. Pending register (EXTI_PD) 8. General-purpose and alternate-function I/Os (GPIO and AFIO) 8.1. Overview 8.2. Characteristics 8.3. Function overview 8.3.1. GPIO pin configuration 8.3.2. External interrupt/event lines 8.3.3. Alternate functions (AF) 8.3.4. Input configuration 8.3.5. Output configuration 8.3.6. Analog configuration 8.3.7. Alternate function (AF) configuration 8.3.8. GPIO locking function 8.3.9. GPIO I/O compensation cell 8.4. Remapping function I/O and debug configuration 8.4.1. Overview 8.4.2. Characteristics 8.4.3. JTAG/SWD alternate function remapping 8.4.4. ADC AF remapping 8.4.5. TIMER AF remapping 8.4.6. USART AF remapping 8.4.7. I2C0 AF remapping 8.4.8. SPI0/SPI2/I2S AF remapping 8.4.9. CTC AF remapping 8.4.10. CLK pins AF remapping 8.5. Register definition 8.5.1. Port control register 0 (GPIOx_CTL0, x=A..E) 8.5.2. Port control register 1 (GPIOx_CTL1, x=A..E) 8.5.3. Port input status register (GPIOx_ISTAT, x=A..E) 8.5.4. Port output control register (GPIOx_OCTL, x=A..E) 8.5.5. Port bit operate register (GPIOx_BOP, x=A..E) 8.5.6. Port bit clear register (GPIOx_BC, x=A..E) 8.5.7. Port configuration lock register (GPIOx_LOCK, x=A..E) 8.5.8. Port bit speed register (GPIOx_SPD, x=A..E) 8.5.9. Event control register (AFIO_EC) 8.5.10. AFIO port configuration register 0 (AFIO_PCF0) 8.5.11. EXTI sources selection register 0 (AFIO_EXTISS0) 8.5.12. EXTI sources selection register 1 (AFIO_EXTISS1) 8.5.13. EXTI sources selection register 2 (AFIO_EXTISS2) 8.5.14. EXTI sources selection register 3 (AFIO_EXTISS3) 8.5.15. AFIO port configuration register 1 (AFIO_PCF1) 8.5.16. IO compensation control register (AFIO_CPSCTL) 9. Cyclic redundancy checks management unit (CRC) 9.1. Overview 9.2. Characteristics 9.3. Function overview 9.4. Register definition 9.4.1. Data register (CRC_DATA) 9.4.2. Free data register (CRC_FDATA) 9.4.3. Control register (CRC_CTL) 10. Direct memory access controller (DMA) 10.1. Overview 10.2. Characteristics 10.3. Block diagram 10.4. Function overview 10.4.1. DMA operation 10.4.2. Peripheral handshake 10.4.3. Arbitration 10.4.4. Address generation 10.4.5. Circular mode 10.4.6. Memory to memory mode 10.4.7. Channel configuration 10.4.8. Interrupt 10.4.9. DMA request mapping 10.5. Register definition 10.5.1. Interrupt flag register (DMA_INTF) 10.5.2. Interrupt flag clear register (DMA_INTC) 10.5.3. Channel x control register (DMA_CHxCTL) 10.5.4. Channel x counter register (DMA_CHxCNT) 10.5.5. Channel x peripheral base address register (DMA_CHxPADDR) 10.5.6. Channel x memory base address register (DMA_CHxMADDR) 11. Debug (DBG) 11.1. Overview 11.2. JTAG/SW function overview 11.2.1. Switch JTAG or SW interface 11.2.2. Pin assignment 11.2.3. JTAG daisy chained structure 11.2.4. Debug reset 11.2.5. JEDEC-106 ID code 11.3. Debug hold function overview 11.3.1. Debug support for power saving mode 11.3.2. Debug support for TIMER, I2C, WWDGT and FWDGT 11.4. Register definition 11.4.1. ID code register (DBG_ID) 11.4.2. Control register (DBG_CTL) 12. Analog-to-digital converter (ADC) 12.1. Overview 12.2. Characteristics 12.3. Pins and internal signals 12.4. Function overview 12.4.1. Foreground calibration function 12.4.2. ADC clock 12.4.3. ADCON enable 12.4.4. Routine sequence 12.4.5. Operation modes Single operation mode Continuous operation mode Scan operation mode Discontinuous operation mode 12.4.6. Conversion result threshold monitor function 12.4.7. Data storage mode 12.4.8. Sample time configuration 12.4.9. External trigger configuration 12.4.10. DMA request 12.4.11. ADC internal channels 12.4.12. Programmable resolution (DRES) 12.4.13. On-chip hardware oversampling 12.5. ADC sync mode 12.5.1. Free mode 12.5.2. Routine parallel mode 12.5.3. Routine follow-up fast mode 12.5.4. Routine follow-up slow mode 12.6. ADC interrupts 12.7. Register definition 12.7.1. Status register (ADC_STAT) 12.7.2. Control register 0 (ADC_CTL0) 12.7.3. Control register 1 (ADC_CTL1) 12.7.4. Sample time register 0 (ADC_SAMPT0) 12.7.5. Sample time register 1 (ADC_SAMPT1) 12.7.6. Watchdog high threshold register (ADC_WDHT) 12.7.7. Watchdog low threshold register (ADC_WDLT) 12.7.8. Routine sequence register 0 (ADC_RSQ0) 12.7.9. Routine sequence register 1 (ADC_RSQ1) 12.7.10. Routine sequence register 2 (ADC_RSQ2) 12.7.11. Routine data register (ADC_RDATA) 12.7.12. Oversample control register (ADC_OVSAMPCTL) 13. Digital-to-analog converter (DAC) 13.1. Overview 13.2. Characteristics 13.3. Function overview 13.3.1. DAC enable 13.3.2. DAC output buffer 13.3.3. DAC data configuration 13.3.4. DAC trigger 13.3.5. DAC conversion 13.3.6. DAC noise wave 13.3.7. DAC output voltage 13.3.8. DMA request 13.3.9. DAC concurrent conversion 13.4. Register definition 13.4.1. DACx control register 0 (DAC_CTL0) 13.4.2. DACx software trigger register (DAC_SWT) 13.4.3. DACx_OUT0 12-bit right-aligned data holding register (DAC_OUT0_R12DH) 13.4.4. DACx_OUT0 12-bit left-aligned data holding register (DAC_OUT0_L12DH) 13.4.5. DACx_OUT0 8-bit right-aligned data holding register (DAC_OUT0_R8DH) 13.4.6. DACx_OUT1 12-bit right-aligned data holding register (DAC_OUT1_R12DH) 13.4.7. DACx_OUT1 12-bit left-aligned data holding register (DAC_OUT1_L12DH) 13.4.8. DACx_OUT1 8-bit right-aligned data holding register (DAC_OUT1_R8DH) 13.4.9. DACx concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) 13.4.10. DACx concurrent mode 12-bit left-aligned data holding register (DACC_L12DH) 13.4.11. DACx concurrent mode 8-bit right-aligned data holding register (DACC_R8DH) 13.4.12. DACx_OUT0 data output register (DAC_OUT0_DO) 13.4.13. DACx_OUT1 data output register (DAC_OUT1_DO) 14. Watchdog timer (WDGT) 14.1. Free watchdog timer (FWDGT) 14.1.1. Overview 14.1.2. Characteristics 14.1.3. Function overview 14.1.4. Register definition Control register (FWDGT_CTL) Prescaler register (FWDGT_PSC) Reload register (FWDGT_RLD) Status register (FWDGT_STAT) 14.2. Window watchdog timer (WWDGT) 14.2.1. Overview 14.2.2. Characteristics 14.2.3. Function overview 14.2.4. Register definition Control register (WWDGT_CTL) Configuration register (WWDGT_CFG) Status register (WWDGT_STAT) 15. Real-time Clock (RTC) 15.1. Overview 15.2. Characteristics 15.3. Function overview 15.3.1. RTC reset 15.3.2. RTC reading 15.3.3. RTC configuration 15.3.4. RTC flag assertion 15.4. Register definition 15.4.1. RTC interrupt enable register(RTC_INTEN) 15.4.2. RTC control register(RTC_CTL) 15.4.3. RTC prescaler high register (RTC_PSCH) 15.4.4. RTC prescaler low register(RTC_PSCL) 15.4.5. RTC divider high register (RTC_DIVH) 15.4.6. RTC divider low register (RTC_DIVL) 15.4.7. RTC counter high register(RTC_CNTH) 15.4.8. RTC counter low register (RTC_CNTL) 15.4.9. RTC alarm high register(RTC_ALRMH) 15.4.10. RTC alarm low register (RTC_ALRML) 16. TIMER 16.1. Advanced timer (TIMERx, x=0, 7) 16.1.1. Overview 16.1.2. Characteristics 16.1.3. Block diagram 16.1.4. Function overview Clock source configuration Clock prescaler Counter up counting Counter down counting Counter center-aligned counting Update event (from overflow/underflow) rate configuration Input capture and output compare channels Output PWM function Channel output prepare signal Channel output complementary PWM Insertion dead time for complementary PWM Break mode Quadrature decoder Hall sensor function Master-slave management Single pulse mode Timers interconnection Timer DMA mode Timer debug mode 16.1.5. TIMERx registers (x=0, 7) Control register 0 (TIMERx_CTL0) Control register 1 (TIMERx_CTL1) Slave mode configuration register (TIMERx_SMCFG) DMA and interrupt enable register (TIMERx_DMAINTEN) Interrupt flag register (TIMERx_INTF) Software event generation register (TIMERx_SWEVG) Channel control register 0 (TIMERx_CHCTL0) Channel control register 1 (TIMERx_CHCTL1) Channel control register 2 (TIMERx_CHCTL2) Counter register (TIMERx_CNT) Prescaler register (TIMERx_PSC) Counter auto reload register (TIMERx_CAR) Counter repetition register (TIMERx_CREP) Channel 0 capture/compare value register (TIMERx_CH0CV) Channel 1 capture/compare value register (TIMERx_CH1CV) Channel 2 capture/compare value register (TIMERx_CH2CV) Channel 3 capture/compare value register (TIMERx_CH3CV) Complementary channel protection register (TIMERx_CCHP) DMA configuration register (TIMERx_DMACFG) DMA transfer buffer register (TIMERx_DMATB) Configuration register (TIMERx_CFG) 16.2. General level0 timer (TIMERx, x=1, 2, 3, 4) 16.2.1. Overview 16.2.2. Characteristics 16.2.3. Block diagram 16.2.4. Function overview Clock source configuration Clock prescaler Counter up counting Counter down counting Counter center-aligned counting Input capture and output compare channels Output PWM function Channel output prepare signal Quadrature decoder Hall sensor function Master-slave management Single pulse mode Timers interconnection Timer DMA mode Timer debug mode 16.2.5. TIMERx registers(x=1, 2, 3, 4) Control register 0 (TIMERx_CTL0) Control register 1 (TIMERx_CTL1) Slave mode configuration register (TIMERx_SMCFG) DMA and interrupt enable register (TIMERx_DMAINTEN) Interrupt flag register (TIMERx_INTF) Software event generation register (TIMERx_SWEVG) Channel control register 0 (TIMERx_CHCTL0) Channel control register 1 (TIMERx_CHCTL1) Channel control register 2 (TIMERx_CHCTL2) Counter register (TIMERx_CNT) Prescaler register (TIMERx_PSC) Counter auto reload register (TIMERx_CAR) Channel 0 capture/compare value register (TIMERx_CH0CV) Channel 1 capture/compare value register (TIMERx_CH1CV) Configuration register (TIMERx_CFG) Channel 2 capture/compare value register (TIMERx_CH2CV) Channel 3 capture/compare value register (TIMERx_CH3CV) DMA configuration register (TIMERx_DMACFG) DMA transfer buffer register (TIMERx_DMATB) 16.3. General level1 timer (TIMERx, x=8, 11) 16.3.1. Overview 16.3.2. Characteristics 16.3.3. Block diagram 16.3.4. Function overview Clock source configuration Clock prescaler Counter up counting Input capture and output compare channels Output PWM function Channel output prepare signal Master-slave management Single pulse mode Timers interconnection Timer debug mode 16.3.5. TIMERx registers (x=8, 11) Control register 0 (TIMERx_CTL0) Slave mode configuration register (TIMERx_SMCFG) Interrupt enable register (TIMERx_DMAINTEN) Interrupt flag register (TIMERx_INTF) Software event generation register (TIMERx_SWEVG) Channel control register 0 (TIMERx_CHCTL0) Channel control register 2 (TIMERx_CHCTL2) Counter register (TIMERx_CNT) Prescaler register (TIMERx_PSC) Counter auto reload register (TIMERx_CAR) Channel 0 capture/compare value register (TIMERx_CH0CV) Channel 1 capture/compare value register (TIMERx_CH1CV) Configuration register (TIMERx_CFG) 16.4. General level2 timer (TIMERx, x=9, 10, 12, 13) 16.4.1. Overview 16.4.2. Characteristics 16.4.3. Block diagram 16.4.4. Function overview Clock source configuration Clock prescaler Counter up counting Input capture and output compare channels Channel output prepare signal Timers interconnection Timer debug mode 16.4.5. TIMERx registers (x=9, 10, 12, 13) Control register 0 (TIMERx_CTL0) Interrupt enable register (TIMERx_DMAINTEN) Interrupt flag register (TIMERx_INTF) Software event generation register (TIMERx_SWEVG) Channel control register 0 (TIMERx_CHCTL0) Channel control register 2 (TIMERx_CHCTL2) Counter register (TIMERx_CNT) Prescaler register (TIMERx_PSC) Counter auto reload register (TIMERx_CAR) Channel 0 capture/compare value register (TIMERx_CH0CV) Configuration register (TIMERx_CFG) 16.5. Basic timer (TIMERx, x=5, 6) 16.5.1. Overview 16.5.2. Characteristics 16.5.3. Block diagram 16.5.4. Function overview Clock source configuration Clock prescaler Counter up counting Single pulse mode Timer debug mode 16.5.5. TIMERx registers (x=5, 6) Control register 0 (TIMERx_CTL0) Control register 1 (TIMERx_CTL1) Interrupt enable register (TIMERx_DMAINTEN) Interrupt flag register (TIMERx_INTF) Software event generation register (TIMERx_SWEVG) Counter register (TIMERx_CNT) Prescaler register (TIMERx_PSC) Counter auto reload register (TIMERx_CAR) 17. Universal synchronous/asynchronous receiver /transmitter (USART) 17.1. Overview 17.2. Characteristics 17.3. Function overview 17.3.1. USART frame format 17.3.2. Baud rate generation 17.3.3. USART transmitter 17.3.4. USART receiver 17.3.5. Use DMA for data buffer access 17.3.6. Hardware flow control RTS flow control CTS flow control 17.3.7. Multi-processor communication 17.3.8. LIN mode 17.3.9. Synchronous mode 17.3.10. IrDA SIR ENDEC mode 17.3.11. Half-duplex communication mode 17.3.12. Smartcard (ISO7816-3) mode Character (T=0) mode Block (T=1) mode Direct and inverse convention 17.3.13. USART interrupts 17.4. Register definition 17.4.1. Status register 0 (USART_STAT0) 17.4.2. Data register (USART_DATA) 17.4.3. Baud rate register (USART_BAUD) 17.4.4. Control register 0 (USART_CTL0) 17.4.5. Control register 1 (USART_CTL1) 17.4.6. Control register 2 (USART_CTL2) 17.4.7. Guard time and prescaler register (USART_GP) 17.4.8. Control register 3 (USART_CTL3) 17.4.9. Receiver timeout register (USART_RT) 17.4.10. Status register 1 (USART_STAT1) 17.4.11. Coherence control register (USART_CHC) 18. Inter-integrated circuit interface (I2C) 18.1. Overview 18.2. Characteristics 18.3. Function overview 18.3.1. SDA and SCL lines 18.3.2. Data validation 18.3.3. START and STOP signal 18.3.4. Clock synchronization 18.3.5. Arbitration 18.3.6. I2C communication flow 18.3.7. Programming model Programming model in slave transmitting mode Programming model in slave receiving mode Programming model in master transmitting mode Programming model in master receiving mode Solution A Solution B 18.3.8. SCL line stretching 18.3.9. Use DMA for data transfer 18.3.10. Packet error checking 18.3.11. SMBus support SMBus protocol Address resolution protocol Time-out feature Packet error checking SMBus alert SMBus programming flow 18.3.12. SAM_V support 18.3.13. Status, errors and interrupts 18.4. Register definition 18.4.1. Control register 0 (I2C_CTL0) 18.4.2. Control register 1 (I2C_CTL1) 18.4.3. Slave address register 0 (I2C_SADDR0) 18.4.4. Slave address register 1 (I2C_SADDR1) 18.4.5. Transfer buffer register (I2C_DATA) 18.4.6. Transfer status register 0 (I2C_STAT0) 18.4.7. Transfer status register 1 (I2C_STAT1) 18.4.8. Clock configure register (I2C_CKCFG) 18.4.9. Rise time register (I2C_RT) 18.4.10. SAM control and status register (I2C_SAMCS) 18.4.11. Fast-mode-plus configure register(I2C_FMPCFG) 19. Serial peripheral interface/Inter-IC sound (SPI/I2S) 19.1. Overview 19.2. Characteristics 19.2.1. SPI characteristics 19.2.2. I2S characteristics 19.3. SPI function overview 19.3.1. SPI block diagram 19.3.2. SPI signal description Normal configuration (not Quad-SPI mode) Quad-SPI configuration 19.3.3. SPI clock timing and data format 19.3.4. NSS function Slave mode Master mode 19.3.5. SPI operating modes SPI initialization sequence SPI basic transmission and reception sequence Transmission sequence Reception sequence SPI operation sequence in different modes (Not Quad-SPI, TI mode or NSSP mode) SPI TI mode NSS pulse mode operation sequence Quad-SPI mode operation sequence Quad write operation Quad read operation SPI disabling sequence MFD SFD MTU MTB STU STB MRU MRB SRU SRB TI mode NSS pulse mode Quad-SPI mode 19.3.6. DMA function 19.3.7. CRC function 19.3.8. SPI interrupts Status flags Error flags 19.4. I2S function overview 19.4.1. I2S block diagram 19.4.2. I2S signal description 19.4.3. I2S audio standards I2S Phillips standard MSB justified standard LSB justified standard PCM standard 19.4.4. I2S clock 19.4.5. Operation Operation modes I2S initialization sequence I2S master transmission sequence I2S master reception sequence I2S slave transmission sequence I2S slave reception sequence 19.4.6. DMA function 19.4.7. I2S interrupts Status flags Error flags 19.5. Register definition 19.5.1. Control register 0 (SPI_CTL0) 19.5.2. Control register 1 (SPI_CTL1) 19.5.3. Status register (SPI_STAT) 19.5.4. Data register (SPI_DATA) 19.5.5. CRC polynomial register (SPI_CRCPOLY) 19.5.6. RX CRC register (SPI_RCRC) 19.5.7. TX CRC register (SPI_TCRC) 19.5.8. I2S control register (SPI_I2SCTL) 19.5.9. I2S clock prescaler register (SPI_I2SPSC) 19.5.10. Quad-SPI mode control register (SPI_QCTL) of SPI0 20. External memory controller (EXMC) 20.1. Overview 20.2. Characteristics 20.3. Function overview 20.3.1. Block diagram 20.3.2. Basic regulation of EXMC access 20.3.3. NOR/PSRAM controller NOR/PSRAM memory device interface description Supported memory access mode NOR Flash/PSRAM controller timing Asynchronous access timing diagram Synchronous access timing 20.4. Register definition 20.4.1. SRAM/NOR Flash control registers (EXMC_SNCTL) 20.4.2. SRAM/NOR Flash timing configuration registers (EXMC_SNTCFG) 20.4.3. SRAM/NOR Flash write timing configuration registers (EXMC_SNWTCFG) 21. Universal serial bus full-speed interface (USBFS) 21.1. Overview 21.2. Characteristics 21.3. Block diagram 21.4. Signal description 21.5. Function overview 21.5.1. USBFS clocks and working modes 21.5.2. USB host function 21.5.3. USB device function 21.5.4. OTG function overview 21.5.5. Data FIFO 21.5.6. Operation guide Host mode Device mode 21.6. Interrupts 21.7. Register definition 21.7.1. Global control and status registers Global OTG control and status register (USBFS_GOTGCS) Global OTG interrupt flag register (USBFS_GOTGINTF) Global AHB control and status register (USBFS_GAHBCS) Global USB control and status register (USBFS_GUSBCS) Global reset control register (USBFS_GRSTCTL) Global interrupt flag register (USBFS_GINTF) Global interrupt enable register (USBFS_GINTEN) Global receive status read/pop registers (USBFS_GRSTATR/USBFS_GRSTATP) Global receive FIFO length register (USBFS_GRFLEN) Host non-periodic Tx FIFO length register/Device IN endpoint 0 Tx FIFO length (USBFS_HNPTFLEN/USBFS_DIEP0TFLEN) Host non-periodic Tx FIFO/queue status register (USBFS_HNPTFQSTAT) Global core configuration register (USBFS_GCCFG) Core ID register (USBFS_CID) Host periodic Tx FIFO length register (USBFS_HPTFLEN) Device IN endpoint Tx FIFO length register (USBFS_DIEPxTFLEN) (x = 1…3, where x is the FIFO_number) 21.7.2. Host control and status registers Host control register (USBFS_HCTL) Host frame interval register (USBFS_HFT) Host frame information remaining register (USBFS_HFINFR) Host periodic Tx FIFO/queue status register (USBFS_HPTFQSTAT) Host all channels interrupt register (USBFS_HACHINT) Host all channels interrupt enable register (USBFS_HACHINTEN) Host port control and status register (USBFS_HPCS) Host channel x control register (USBFS_HCHxCTL) (x = 0…7 where x = channel_number) Host channel x interrupt flag register (USBFS_HCHxINTF) (x = 0...7 where x = channel_number) Host channel x interrupt enable register (USBFS_HCHxINTEN) (x = 0…7, where x = channel_number) Host channel x transfer length register (USBFS_HCHxLEN) (x = 0…7, where x = channel_number) 21.7.3. Device control and status registers Device configuration register (USBFS_DCFG) Device control register (USBFS_DCTL) Device status register (USBFS_DSTAT) Device IN endpoint common interrupt enable register (USBFS_DIEPINTEN) Device OUT endpoint common interrupt enable register (USBFS_DOEPINTEN) Device all endpoints interrupt register (USBFS_DAEPINT) Device all endpoints interrupt enable register (USBFS_DAEPINTEN) Device VBUS discharge time register (USBFS_DVBUSDT) Device VBUS pulsing time register (USBFS_DVBUSPT) Device IN endpoint FIFO empty interrupt enable register (USBFS_DIEPFEINTEN) Device IN endpoint 0 control register (USBFS_DIEP0CTL) Device IN endpoint x control register (USBFS_DIEPxCTL) (x = 1…3, where x = endpoint_number) Device OUT endpoint 0 control register (USBFS_DOEP0CTL) Device OUT endpoint x control register (USBFS_DOEPxCTL) (x = 1…3, where x = endpoint_number) Device IN endpoint x interrupt flag register (USBFS_DIEPxINTF) (x = 0...3, where x = endpoint_number) Device OUT endpoint x interrupt flag register (USBFS_DOEPxINTF) (x = 0...3, where x = endpoint_number) Device IN endpoint 0 transfer length register (USBFS_DIEP0LEN) Device OUT endpoint 0 transfer length register (USBFS_DOEP0LEN) Device IN endpoint x transfer length register (USBFS_DIEPxLEN) (x = 1…3, where x = endpoint_number) Device OUT endpoint x transfer length register (USBFS_DOEPxLEN) (x = 1…3, where x = endpoint_number) Device IN endpoint x Tx FIFO status register (USBFS_DIEPxTFSTAT) (x = 0…3, where x = endpoint_number) 21.7.4. Power and clock control register (USBFS_PWRCLKCTL) 22. Appendix 22.1. List of abbreviations used in register 22.2. List of terms 22.3. Available peripherals 23. Revision history